From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/samsung/exynos5250/clock_init.c | 248 ++++++++++++++++---------------- 1 file changed, 124 insertions(+), 124 deletions(-) (limited to 'src/soc/samsung/exynos5250/clock_init.c') diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index fa19eb1763..ca3dbd9921 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -28,27 +28,27 @@ void system_clock_init(struct mem_timings *mem, /* Turn on the MCT as early as possible. */ exynos_mct->g_tcon |= (1 << 8); - clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); + clrbits32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cpu); } while ((val | MUX_APLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); + clrbits32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { val = read32(&exynos_clock->mux_stat_top2); } while ((val | tmp) != val); - clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); + clrbits32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cdrex); } while ((val | MUX_BPLL_SEL_MASK) != val); @@ -94,7 +94,7 @@ void system_clock_init(struct mem_timings *mem, } while (0 != val); /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + clrbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set APLL */ write32(&exynos_clock->apll_con1, APLL_CON1_VAL); @@ -105,7 +105,7 @@ void system_clock_init(struct mem_timings *mem, ; /* now it is safe to switch to APLL */ - setbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + setbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set MPLL */ write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); @@ -118,7 +118,7 @@ void system_clock_init(struct mem_timings *mem, * Configure MUX_MPLL_FOUT to choose the direct clock source * path and avoid the fixed DIV/2 block to save power */ - setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); /* Set BPLL */ if (mem->use_bpll) { @@ -128,7 +128,7 @@ void system_clock_init(struct mem_timings *mem, while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; - setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); } /* Set CPLL */ @@ -280,124 +280,124 @@ void system_clock_init(struct mem_timings *mem, void clock_gate(void) { /* CLK_GATE_IP_SYSRGT */ - clrbits_le32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); + clrbits32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); /* CLK_GATE_IP_ACP */ - clrbits_le32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | - CLK_SMMUSSS_MASK | - CLK_SMMUMDMA_MASK | - CLK_ID_REMAPPER_MASK | - CLK_G2D_MASK | - CLK_SSS_MASK | - CLK_MDMA_MASK | - CLK_SECJTAG_MASK); + clrbits32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | + CLK_SMMUSSS_MASK | + CLK_SMMUMDMA_MASK | + CLK_ID_REMAPPER_MASK | + CLK_G2D_MASK | + CLK_SSS_MASK | + CLK_MDMA_MASK | + CLK_SECJTAG_MASK); /* CLK_GATE_BUS_SYSLFT */ - clrbits_le32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); + clrbits32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); /* CLK_GATE_IP_ISP0 */ - clrbits_le32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | - CLK_WDT_ISP_MASK | - CLK_PWM_ISP_MASK | - CLK_MTCADC_ISP_MASK | - CLK_I2C1_ISP_MASK | - CLK_I2C0_ISP_MASK | - CLK_MPWM_ISP_MASK | - CLK_MCUCTL_ISP_MASK | - CLK_INT_COMB_ISP_MASK | - CLK_SMMU_MCUISP_MASK | - CLK_SMMU_SCALERP_MASK | - CLK_SMMU_SCALERC_MASK | - CLK_SMMU_FD_MASK | - CLK_SMMU_DRC_MASK | - CLK_SMMU_ISP_MASK | - CLK_GICISP_MASK | - CLK_ARM9S_MASK | - CLK_MCUISP_MASK | - CLK_SCALERP_MASK | - CLK_SCALERC_MASK | - CLK_FD_MASK | - CLK_DRC_MASK | - CLK_ISP_MASK); + clrbits32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | + CLK_WDT_ISP_MASK | + CLK_PWM_ISP_MASK | + CLK_MTCADC_ISP_MASK | + CLK_I2C1_ISP_MASK | + CLK_I2C0_ISP_MASK | + CLK_MPWM_ISP_MASK | + CLK_MCUCTL_ISP_MASK | + CLK_INT_COMB_ISP_MASK | + CLK_SMMU_MCUISP_MASK | + CLK_SMMU_SCALERP_MASK | + CLK_SMMU_SCALERC_MASK | + CLK_SMMU_FD_MASK | + CLK_SMMU_DRC_MASK | + CLK_SMMU_ISP_MASK | + CLK_GICISP_MASK | + CLK_ARM9S_MASK | + CLK_MCUISP_MASK | + CLK_SCALERP_MASK | + CLK_SCALERC_MASK | + CLK_FD_MASK | + CLK_DRC_MASK | + CLK_ISP_MASK); /* CLK_GATE_IP_ISP1 */ - clrbits_le32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | - CLK_SPI0_ISP_MASK | - CLK_SMMU3DNR_MASK | - CLK_SMMUDIS1_MASK | - CLK_SMMUDIS0_MASK | - CLK_SMMUODC_MASK | - CLK_3DNR_MASK | - CLK_DIS_MASK | - CLK_ODC_MASK); + clrbits32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | + CLK_SPI0_ISP_MASK | + CLK_SMMU3DNR_MASK | + CLK_SMMUDIS1_MASK | + CLK_SMMUDIS0_MASK | + CLK_SMMUODC_MASK | + CLK_3DNR_MASK | + CLK_DIS_MASK | + CLK_ODC_MASK); /* CLK_GATE_SCLK_ISP */ - clrbits_le32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); + clrbits32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); /* CLK_GATE_IP_GSCL */ - clrbits_le32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | - CLK_SMMUFIMC_LITE1_MASK | - CLK_SMMUFIMC_LITE0_MASK | - CLK_SMMUGSCL3_MASK | - CLK_SMMUGSCL2_MASK | - CLK_SMMUGSCL1_MASK | - CLK_SMMUGSCL0_MASK | - CLK_GSCL_WRAP_B_MASK | - CLK_GSCL_WRAP_A_MASK | - CLK_CAMIF_TOP_MASK | - CLK_GSCL3_MASK | - CLK_GSCL2_MASK | - CLK_GSCL1_MASK | - CLK_GSCL0_MASK); + clrbits32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | + CLK_SMMUFIMC_LITE1_MASK | + CLK_SMMUFIMC_LITE0_MASK | + CLK_SMMUGSCL3_MASK | + CLK_SMMUGSCL2_MASK | + CLK_SMMUGSCL1_MASK | + CLK_SMMUGSCL0_MASK | + CLK_GSCL_WRAP_B_MASK | + CLK_GSCL_WRAP_A_MASK | + CLK_CAMIF_TOP_MASK | + CLK_GSCL3_MASK | + CLK_GSCL2_MASK | + CLK_GSCL1_MASK | + CLK_GSCL0_MASK); /* CLK_GATE_IP_DISP1 */ - clrbits_le32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | - CLK_ASYNCTVX_MASK | - CLK_HDMI_MASK | - CLK_MIXER_MASK | - CLK_DSIM1_MASK); + clrbits32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | + CLK_ASYNCTVX_MASK | + CLK_HDMI_MASK | + CLK_MIXER_MASK | + CLK_DSIM1_MASK); /* CLK_GATE_IP_MFC */ - clrbits_le32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | - CLK_SMMUMFCL_MASK | - CLK_MFC_MASK); + clrbits32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | + CLK_SMMUMFCL_MASK | + CLK_MFC_MASK); /* CLK_GATE_IP_GEN */ - clrbits_le32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | - CLK_SMMUJPEG_MASK | - CLK_SMMUROTATOR_MASK | - CLK_MDMA1_MASK | - CLK_JPEG_MASK | - CLK_ROTATOR_MASK); + clrbits32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | + CLK_SMMUJPEG_MASK | + CLK_SMMUROTATOR_MASK | + CLK_MDMA1_MASK | + CLK_JPEG_MASK | + CLK_ROTATOR_MASK); /* CLK_GATE_IP_FSYS */ - clrbits_le32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | - CLK_SMMUMCU_IOP_MASK | - CLK_SATA_PHY_I2C_MASK | - CLK_SATA_PHY_CTRL_MASK | - CLK_MCUCTL_MASK | - CLK_NFCON_MASK | - CLK_SMMURTIC_MASK | - CLK_RTIC_MASK | - CLK_MIPI_HSI_MASK | - CLK_USBOTG_MASK | - CLK_SATA_MASK | - CLK_PDMA1_MASK | - CLK_PDMA0_MASK | - CLK_MCU_IOP_MASK); + clrbits32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | + CLK_SMMUMCU_IOP_MASK | + CLK_SATA_PHY_I2C_MASK | + CLK_SATA_PHY_CTRL_MASK | + CLK_MCUCTL_MASK | + CLK_NFCON_MASK | + CLK_SMMURTIC_MASK | + CLK_RTIC_MASK | + CLK_MIPI_HSI_MASK | + CLK_USBOTG_MASK | + CLK_SATA_MASK | + CLK_PDMA1_MASK | + CLK_PDMA0_MASK | + CLK_MCU_IOP_MASK); /* CLK_GATE_IP_PERIC */ - clrbits_le32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | - CLK_HS_I2C2_MASK | - CLK_HS_I2C1_MASK | - CLK_HS_I2C0_MASK | - CLK_AC97_MASK | - CLK_SPDIF_MASK | - CLK_PCM2_MASK | - CLK_PCM1_MASK | - CLK_I2S2_MASK | - CLK_SPI2_MASK | - CLK_SPI0_MASK); + clrbits32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | + CLK_HS_I2C2_MASK | + CLK_HS_I2C1_MASK | + CLK_HS_I2C0_MASK | + CLK_AC97_MASK | + CLK_SPDIF_MASK | + CLK_PCM2_MASK | + CLK_PCM1_MASK | + CLK_I2S2_MASK | + CLK_SPI2_MASK | + CLK_SPI0_MASK); /* * CLK_GATE_IP_PERIS @@ -405,33 +405,33 @@ void clock_gate(void) * register (PRO_ID) works correctly when the OS kernel determines * which chip it is running on. */ - clrbits_le32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | - CLK_TZPC9_MASK | - CLK_TZPC8_MASK | - CLK_TZPC7_MASK | - CLK_TZPC6_MASK | - CLK_TZPC5_MASK | - CLK_TZPC4_MASK | - CLK_TZPC3_MASK | - CLK_TZPC2_MASK | - CLK_TZPC1_MASK | - CLK_TZPC0_MASK); + clrbits32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | + CLK_TZPC9_MASK | + CLK_TZPC8_MASK | + CLK_TZPC7_MASK | + CLK_TZPC6_MASK | + CLK_TZPC5_MASK | + CLK_TZPC4_MASK | + CLK_TZPC3_MASK | + CLK_TZPC2_MASK | + CLK_TZPC1_MASK | + CLK_TZPC0_MASK); /* CLK_GATE_BLOCK */ - clrbits_le32(&exynos_clock->gate_block, CLK_ACP_MASK); + clrbits32(&exynos_clock->gate_block, CLK_ACP_MASK); /* CLK_GATE_IP_CDREX */ - clrbits_le32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | - CLK_DPHY1_MASK | - CLK_TZASC_DRBXR_MASK); + clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | + CLK_DPHY1_MASK | + CLK_TZASC_DRBXR_MASK); } void clock_init_dp_clock(void) { /* DP clock enable */ - setbits_le32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); + setbits32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); /* We run DP at 267 Mhz */ - setbits_le32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); + setbits32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -- cgit v1.2.3