From 7dbf9c6747ccdfa8b993d3843a22722742957611 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 30 Jul 2015 18:49:48 -0700 Subject: edid: Use edid_mode struct to reduce redundancy This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang Original-Reviewed-by: Julius Werner Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/rockchip/rk3288/display.c | 8 ++++---- src/soc/rockchip/rk3288/hdmi.c | 36 ++++++++++++++++++------------------ src/soc/rockchip/rk3288/vop.c | 32 ++++++++++++++++---------------- 3 files changed, 38 insertions(+), 38 deletions(-) (limited to 'src/soc/rockchip') diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index d241e3ea13..02526a4625 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -93,15 +93,15 @@ void rk_display_init(device_t dev, u32 lcdbase, return; } - if (rkclk_configure_vop_dclk(conf->vop_id, edid.pixel_clock * KHz)) { + if (rkclk_configure_vop_dclk(conf->vop_id, edid.mode.pixel_clock * KHz)) { printk(BIOS_WARNING, "config vop err\n"); return; } edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel; - edid.bytes_per_line = edid.ha * conf->framebuffer_bits_per_pixel / 8; - edid.x_resolution = edid.ha; - edid.y_resolution = edid.va; + edid.bytes_per_line = edid.mode.ha * conf->framebuffer_bits_per_pixel / 8; + edid.x_resolution = edid.mode.ha; + edid.y_resolution = edid.mode.va; rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid); diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index 582c834c5c..a7a9c400d3 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -494,11 +494,11 @@ static void hdmi_av_composer(const struct edid *edid) /* set up hdmi_fc_invidconf */ inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE; - inv_val |= ((edid->pvsync == '+') ? + inv_val |= ((edid->mode.pvsync == '+') ? HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); - inv_val |= ((edid->phsync == '+') ? + inv_val |= ((edid->mode.phsync == '+') ? HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); @@ -517,33 +517,33 @@ static void hdmi_av_composer(const struct edid *edid) write32(&hdmi_regs->fc_invidconf, inv_val); /* set up horizontal active pixel width */ - write32(&hdmi_regs->fc_inhactv1, edid->ha >> 8); - write32(&hdmi_regs->fc_inhactv0, edid->ha); + write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8); + write32(&hdmi_regs->fc_inhactv0, edid->mode.ha); /* set up vertical active lines */ - write32(&hdmi_regs->fc_invactv1, edid->va >> 8); - write32(&hdmi_regs->fc_invactv0, edid->va); + write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8); + write32(&hdmi_regs->fc_invactv0, edid->mode.va); /* set up horizontal blanking pixel region width */ - write32(&hdmi_regs->fc_inhblank1, edid->hbl >> 8); - write32(&hdmi_regs->fc_inhblank0, edid->hbl); + write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8); + write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl); /* set up vertical blanking pixel region width */ - write32(&hdmi_regs->fc_invblank, edid->vbl); + write32(&hdmi_regs->fc_invblank, edid->mode.vbl); /* set up hsync active edge delay width (in pixel clks) */ - write32(&hdmi_regs->fc_hsyncindelay1, edid->hso >> 8); - write32(&hdmi_regs->fc_hsyncindelay0, edid->hso); + write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8); + write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso); /* set up vsync active edge delay (in lines) */ - write32(&hdmi_regs->fc_vsyncindelay, edid->vso); + write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso); /* set up hsync active pulse width (in pixel clks) */ - write32(&hdmi_regs->fc_hsyncinwidth1, edid->hspw >> 8); - write32(&hdmi_regs->fc_hsyncinwidth0, edid->hspw); + write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8); + write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw); /* set up vsync active edge delay (in lines) */ - write32(&hdmi_regs->fc_vsyncinwidth, edid->vspw); + write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw); } /* hdmi initialization step b.4 */ @@ -613,11 +613,11 @@ static int hdmi_setup(const struct edid *edid) int ret; hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n", - edid->pixel_clock, edid->ha, edid->va); + edid->mode.pixel_clock, edid->mode.ha, edid->mode.va); hdmi_av_composer(edid); - ret = hdmi_phy_init(edid->pixel_clock); + ret = hdmi_phy_init(edid->mode.pixel_clock); if (ret) return ret; @@ -625,7 +625,7 @@ static int hdmi_setup(const struct edid *edid) hdmi_audio_fifo_reset(); hdmi_audio_set_format(); - hdmi_audio_set_samplerate(edid->pixel_clock); + hdmi_audio_set_samplerate(edid->mode.pixel_clock); hdmi_video_packetize(); hdmi_video_csc(); diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c index 30b73c2d40..784c6c7fa2 100644 --- a/src/soc/rockchip/rk3288/vop.c +++ b/src/soc/rockchip/rk3288/vop.c @@ -39,12 +39,12 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) { u32 lb_mode; u32 rgb_mode; - u32 hactive = edid->ha; - u32 vactive = edid->va; - u32 hsync_len = edid->hspw; - u32 hback_porch = edid->hbl - edid->hso - edid->hspw; - u32 vsync_len = edid->vspw; - u32 vback_porch = edid->vbl - edid->vso - edid->vspw; + u32 hactive = edid->mode.ha; + u32 vactive = edid->mode.va; + u32 hsync_len = edid->mode.hspw; + u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw; + u32 vsync_len = edid->mode.vspw; + u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw; u32 xpos = 0, ypos = 0; struct rk3288_vop_regs *preg = vop_regs[vop_id]; @@ -98,14 +98,14 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) { - u32 hactive = edid->ha; - u32 vactive = edid->va; - u32 hfront_porch = edid->hso; - u32 hsync_len = edid->hspw; - u32 hback_porch = edid->hbl - edid->hso - edid->hspw; - u32 vfront_porch = edid->vso; - u32 vsync_len = edid->vspw; - u32 vback_porch = edid->vbl - edid->vso - edid->vspw; + u32 hactive = edid->mode.ha; + u32 vactive = edid->mode.va; + u32 hfront_porch = edid->mode.hso; + u32 hsync_len = edid->mode.hspw; + u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw; + u32 vfront_porch = edid->mode.vso; + u32 vsync_len = edid->mode.vspw; + u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw; struct rk3288_vop_regs *preg = vop_regs[vop_id]; switch (mode) { @@ -125,8 +125,8 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, V_DSP_OUT_MODE(15) | - V_DSP_HSYNC_POL(edid->phsync == '+') | - V_DSP_VSYNC_POL(edid->pvsync == '+')); + V_DSP_HSYNC_POL(edid->mode.phsync == '+') | + V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); -- cgit v1.2.3