From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/rockchip/common/edp.c | 26 +-- src/soc/rockchip/common/gpio.c | 26 +-- src/soc/rockchip/common/pwm.c | 2 +- src/soc/rockchip/common/spi.c | 14 +- src/soc/rockchip/common/vop.c | 38 ++--- src/soc/rockchip/rk3288/hdmi.c | 92 +++++----- src/soc/rockchip/rk3288/sdram.c | 108 ++++++------ src/soc/rockchip/rk3288/software_i2c.c | 8 +- src/soc/rockchip/rk3288/tsadc.c | 8 +- src/soc/rockchip/rk3399/clock.c | 6 +- src/soc/rockchip/rk3399/saradc.c | 10 +- src/soc/rockchip/rk3399/sdram.c | 300 ++++++++++++++++----------------- src/soc/rockchip/rk3399/tsadc.c | 6 +- src/soc/rockchip/rk3399/usb.c | 12 +- 14 files changed, 328 insertions(+), 328 deletions(-) (limited to 'src/soc/rockchip') diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index ea0930a058..18afc3a50a 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -97,7 +97,7 @@ static void rk_edp_init_interrupt(struct rk_edp *edp) static void rk_edp_enable_sw_function(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, SW_FUNC_EN_N); + clrbits32(&edp->regs->func_en_1, SW_FUNC_EN_N); } static int rk_edp_get_pll_lock_status(struct rk_edp *edp) @@ -116,7 +116,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG); - clrbits_le32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); + clrbits32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -128,7 +128,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | + clrbits32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N | SSC_FUNC_EN_N); } @@ -139,20 +139,20 @@ static void rk_edp_init_aux(struct rk_edp *edp) write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ - setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + setbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1)); /* Enable AUX channel module */ - clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + clrbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); } static int rk_edp_aux_enable(struct rk_edp *edp) { struct stopwatch sw; - setbits_le32(&edp->regs->aux_ch_ctl_2, AUX_EN); + setbits32(&edp->regs->aux_ch_ctl_2, AUX_EN); stopwatch_init_msecs_expire(&sw, 20); do { if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN)) @@ -698,7 +698,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, write32(&edp->regs->buf_data_ctl, val); /* Set normal AUX CH command */ - clrbits_le32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); + clrbits32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); /* * If Rx sends defer, Tx sends only reads @@ -816,7 +816,7 @@ static void rk_edp_init_video(struct rk_edp *edp) static void rk_edp_config_video_slave_mode(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, + clrbits32(&edp->regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); } @@ -828,7 +828,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, u32 val; if (type == REGISTER_M) { - setbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + setbits32(&edp->regs->sys_ctl_4, FIX_M_VID); val = m_value & 0xff; write32(&edp->regs->m_vid_0, val); val = (m_value >> 8) & 0xff; @@ -843,7 +843,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, val = (n_value >> 16) & 0xff; write32(&edp->regs->n_vid_2, val); } else { - clrbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + clrbits32(&edp->regs->sys_ctl_4, FIX_M_VID); write32(&edp->regs->n_vid_0, 0x00); write32(&edp->regs->n_vid_1, 0x80); @@ -914,10 +914,10 @@ static int rk_edp_config_video(struct rk_edp *edp) rk_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0); /* For video bist, Video timing must be generated by register */ - clrbits_le32(&edp->regs->video_ctl_10, F_SEL); + clrbits32(&edp->regs->video_ctl_10, F_SEL); /* Disable video mute */ - clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); + clrbits32(&edp->regs->video_ctl_1, VIDEO_MUTE); return 0; } @@ -1000,7 +1000,7 @@ int rk_edp_prepare(void) int rk_edp_enable(void) { /* Enable video at next frame */ - setbits_le32(&rk_edp.regs->video_ctl_1, VIDEO_EN); + setbits32(&rk_edp.regs->video_ctl_1, VIDEO_EN); return rk_edp_is_video_stream_on(&rk_edp); } diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 3d7e1614e0..16ab385b03 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -24,16 +24,16 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr, - 1 << gpio.num, dir << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_ddr, + 1 << gpio.num, dir << gpio.num); } static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288)) - clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), - pull_val << (gpio.idx * 2)); + clrsetbits32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), + pull_val << (gpio.idx * 2)); else write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), pull_val << (gpio.idx * 2))); @@ -83,13 +83,13 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull) case IRQ_TYPE_LEVEL_LOW: break; } - clrsetbits_le32(&gpio_port[gpio.port]->int_polarity, - mask, int_polarity); - clrsetbits_le32(&gpio_port[gpio.port]->inttype_level, - mask, inttype_level); + clrsetbits32(&gpio_port[gpio.port]->int_polarity, + mask, int_polarity); + clrsetbits32(&gpio_port[gpio.port]->inttype_level, + mask, inttype_level); - setbits_le32(&gpio_port[gpio.port]->inten, mask); - clrbits_le32(&gpio_port[gpio.port]->intmask, mask); + setbits32(&gpio_port[gpio.port]->inten, mask); + clrbits32(&gpio_port[gpio.port]->intmask, mask); } int gpio_irq_status(gpio_t gpio) @@ -100,7 +100,7 @@ int gpio_irq_status(gpio_t gpio) if (!(int_status & mask)) return 0; - setbits_le32(&gpio_port[gpio.port]->porta_eoi, mask); + setbits32(&gpio_port[gpio.port]->porta_eoi, mask); return 1; } @@ -111,8 +111,8 @@ int gpio_get(gpio_t gpio) void gpio_set(gpio_t gpio, int value) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, - !!value << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, + !!value << gpio.num); } void gpio_output(gpio_t gpio, int value) diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index e5da05e672..82fc2596c0 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -79,5 +79,5 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) write32(&rk_pwm->pwm[id].pwm_period_hpr, period); write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty); - setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); + setbits32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); } diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 0307e24d35..d91bae0eac 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -70,13 +70,13 @@ static struct rockchip_spi_slave *to_rockchip_spi(const struct spi_slave *slave) static void spi_cs_activate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - setbits_le32(®s->ser, 1); + setbits32(®s->ser, 1); } static void spi_cs_deactivate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - clrbits_le32(®s->ser, 1); + clrbits32(®s->ser, 1); } static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) @@ -141,8 +141,8 @@ void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) /* Rxd Sample Delay */ rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); assert(rsd <= 3); - clrsetbits_le32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, - rsd << SPI_RXDSD_OFFSET); + clrsetbits32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, + rsd << SPI_RXDSD_OFFSET); } static int spi_ctrlr_claim_bus(const struct spi_slave *slave) @@ -172,7 +172,7 @@ static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) { - clrsetbits_le32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, + clrsetbits32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, tmod << SPI_TMOD_OFFSET); } @@ -275,9 +275,9 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } mask = SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET; if (use_16bit) - clrbits_le32(®s->ctrlr0, mask); + clrbits32(®s->ctrlr0, mask); else - setbits_le32(®s->ctrlr0, mask); + setbits32(®s->ctrlr0, mask); /* Enable/disable transmitter and receiver as needed to * avoid sending or reading spurious bits. */ diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 9c70b78171..6e0ce4086c 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -60,7 +60,7 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1)); - clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, + clrsetbits32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); @@ -89,10 +89,10 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) else lb_mode = LB_RGB_1280X8; - clrsetbits_le32(&preg->win0_ctrl0, - M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, - V_WIN0_LB_MODE(lb_mode) | - V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); + clrsetbits32(&preg->win0_ctrl0, + M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, + V_WIN0_LB_MODE(lb_mode) | + V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); } void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) @@ -111,34 +111,34 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) switch (mode) { case VOP_MODE_HDMI: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); dsp_out_mode = 15; break; case VOP_MODE_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_DUAL_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_EDP: default: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_EDP_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_EDP_OUT_EN(1)); dsp_out_mode = 15; break; } - clrsetbits_le32(&preg->dsp_ctrl0, - M_DSP_OUT_MODE | M_DSP_VSYNC_POL | - M_DSP_HSYNC_POL, - V_DSP_OUT_MODE(dsp_out_mode) | - V_DSP_HSYNC_POL(edid->mode.phsync == '+') | - V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); + clrsetbits32(&preg->dsp_ctrl0, + M_DSP_OUT_MODE | M_DSP_VSYNC_POL | + M_DSP_HSYNC_POL, + V_DSP_OUT_MODE(dsp_out_mode) | + V_DSP_HSYNC_POL(edid->mode.phsync == '+') | + V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index b4de270fc5..6569d295ea 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -250,8 +250,8 @@ static void hdmi_update_csc_coeffs(void) } } - clrsetbits_le32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, - csc_scale); + clrsetbits32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, + csc_scale); } static void hdmi_video_csc(void) @@ -261,8 +261,8 @@ static void hdmi_video_csc(void) /* configure the csc registers */ write32(&hdmi_regs->csc_cfg, interpolation); - clrsetbits_le32(&hdmi_regs->csc_scale, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); + clrsetbits32(&hdmi_regs->csc_scale, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); hdmi_update_csc_coeffs(); } @@ -281,18 +281,18 @@ static void hdmi_video_packetize(void) HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); write32(&hdmi_regs->vp_pr_cd, val); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); /* data from pixel repeater block */ vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | - HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | + HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, - 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, + 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); write32(&hdmi_regs->vp_remap, remap_size); @@ -300,23 +300,23 @@ static void hdmi_video_packetize(void) HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_DISABLE; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | - HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, - vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | + HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, + vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | - HDMI_VP_STUFF_YCC422_STUFFING_MASK, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | + HDMI_VP_STUFF_YCC422_STUFFING_MASK, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, - output_select); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, + output_select); } static inline void hdmi_phy_test_clear(u8 bit) { - clrsetbits_le32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, - bit << HDMI_PHY_TST0_TSTCLR_OFFSET); + clrsetbits32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, + bit << HDMI_PHY_TST0_TSTCLR_OFFSET); } static int hdmi_phy_wait_i2c_done(u32 msec) @@ -352,46 +352,46 @@ static void hdmi_phy_i2c_write(u16 data, u8 addr) static void hdmi_phy_enable_power(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, - enable << HDMI_PHY_CONF0_PDZ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, + enable << HDMI_PHY_CONF0_PDZ_OFFSET); } static void hdmi_phy_enable_tmds(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, - enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, + enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); } static void hdmi_phy_enable_spare(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, - enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, + enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); } static void hdmi_phy_gen2_pddq(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, - enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, + enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); } static void hdmi_phy_gen2_txpwron(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, - enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, + enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); } static void hdmi_phy_sel_data_en_pol(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_SELDATAENPOL_MASK, - enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_SELDATAENPOL_MASK, + enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); } static void hdmi_phy_sel_interface_control(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, - enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, + enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); } static int hdmi_phy_configure(u32 mpixelclock) @@ -723,8 +723,8 @@ static int hdmi_ddc_wait_i2c_done(int msec) static void hdmi_ddc_reset(void) { - clrsetbits_le32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, - HDMI_I2CM_SOFTRSTZ); + clrsetbits32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, + HDMI_I2CM_SOFTRSTZ); } static int hdmi_read_edid(int block, u8 *buff) @@ -737,7 +737,7 @@ static int hdmi_read_edid(int block, u8 *buff) /* set ddc i2c clk which devided from ddc_clk to 100khz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); - clrsetbits_le32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, + clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV_STD_MODE); write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR); @@ -751,13 +751,13 @@ static int hdmi_read_edid(int block, u8 *buff) write32(&hdmi_regs->i2cmess, shift + 8 * n); if (block == 0) - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8, - HDMI_I2CM_OPT_RD8); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8, + HDMI_I2CM_OPT_RD8); else - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8_EXT, - HDMI_I2CM_OPT_RD8_EXT); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8_EXT, + HDMI_I2CM_OPT_RD8_EXT); if (hdmi_ddc_wait_i2c_done(10)) { hdmi_ddc_reset(); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 74038b078e..3305263458 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -522,14 +522,14 @@ static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; rkclk_ddr_reset(channel, 1, 1); udelay(1); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); rkclk_ddr_reset(channel, 1, 0); @@ -544,23 +544,23 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; if (freq <= 250*MHz) { if (freq <= 150*MHz) - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); else - setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + setbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + setbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } else { - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + clrbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } } @@ -637,7 +637,7 @@ static void pctl_cfg(u32 channel, break; } - setbits_le32(&ddr_pctl_regs->scfg, 1); + setbits32(&ddr_pctl_regs->scfg, 1); } static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) @@ -668,33 +668,33 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) switch (sdram_params->dramtype) { case LPDDR3: - clrsetbits_le32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) + clrsetbits32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) | PGCR_DFTCMP(0) | PGCR_DQSCFG(1) | PGCR_ITMDMD(0)); /* DDRMODE select LPDDR3 */ - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_LPDDR2_LPDDR3)); - clrsetbits_le32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, + clrsetbits32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, DQSRES_CFG(4) | DQSNRES_CFG(0xc)); i = TDQSCKMAX_VAL(read32(&ddr_publ_regs->dtpr[1])) - TDQSCK_VAL(read32(&ddr_publ_regs->dtpr[1])); - clrsetbits_le32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, + clrsetbits32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, DQSGE_CFG(i) | DQSGX_CFG(i)); break; case DDR3: - clrbits_le32(&ddr_publ_regs->pgcr, 0x1f); - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrbits32(&ddr_publ_regs->pgcr, 0x1f); + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_DDR3)); break; } if (sdram_params->odt) { /*dynamic RTT enable */ for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + setbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } else { /*dynamic RTT disable */ for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + clrbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } @@ -702,7 +702,7 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs) { - setbits_le32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST + setbits32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & @@ -723,10 +723,10 @@ static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank, static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs, u32 dramtype) { - setbits_le32(&ddr_publ_regs->pir, - (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP - | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC - | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + setbits32(&ddr_publ_regs->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) != (PGSR_IDONE | PGSR_DLDONE)) @@ -775,42 +775,42 @@ static void set_bandwidth_ratio(u32 channel, u32 n) struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; if (n == 1) { - setbits_le32(&ddr_pctl_regs->ppcfg, 1); + setbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_SETBITS(1 << (8 + channel))); - setbits_le32(&msch_regs->ddrtiming, 1 << 31); + setbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte disable*/ - clrbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - clrbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*disable DLL */ - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); } else { - clrbits_le32(&ddr_pctl_regs->ppcfg, 1); + clrbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << (8 + channel))); - clrbits_le32(&msch_regs->ddrtiming, 1 << 31); + clrbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte enable*/ - setbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - setbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*enable DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); /* reset DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); } - setbits_le32(&ddr_pctl_regs->dfistcfg0, 1 << 2); + setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2); } @@ -829,19 +829,19 @@ static int data_training(u32 channel, write32(&ddr_pctl_regs->trefi, 0); if (sdram_params->dramtype != LPDDR3) - setbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + setbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); rank = sdram_params->ch[channel].rank | 1; for (j = 0; j < ARRAY_SIZE(step); j++) { /* * trigger QSTRN and RVTRN * clear DTDONE status */ - setbits_le32(&ddr_publ_regs->pir, PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, PIR_CLRSR); /* trigger DTT */ - setbits_le32(&ddr_publ_regs->pir, - PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | - PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); udelay(1); /* wait echo byte DTDONE */ while ((read32(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank) @@ -869,7 +869,7 @@ static int data_training(u32 channel, send_command(ddr_pctl_regs, rank, REF_CMD, 0); if (sdram_params->dramtype != LPDDR3) - clrbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + clrbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); /* resume auto refresh */ write32(&ddr_pctl_regs->trefi, sdram_params->pctl_timing.trefi); @@ -928,9 +928,9 @@ static void dram_cfg_rbc(u32 chnum, struct rk3288_msch_regs *msch_regs = rk3288_msch[chnum]; if (sdram_params->ch[chnum].bk == 3) - clrsetbits_le32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); + clrsetbits32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); else - clrbits_le32(&ddr_publ_regs->dcr, PDQ_MSK); + clrbits32(&ddr_publ_regs->dcr, PDQ_MSK); write32(&msch_regs->ddrconf, sdram_params->ddrconfig); } @@ -1029,8 +1029,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) * CS1, n=2 * CS0 & CS1, n = 3 */ - clrsetbits_le32(&ddr_publ_regs->pgcr, 0xF << 18, - (sdram_params->ch[channel].rank | 1) << 18); + clrsetbits32(&ddr_publ_regs->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); /* DS=40ohm,ODT=155ohm */ zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2) | PU_OUTPUT(0x19) | PD_OUTPUT(0x19); diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index 8c439842c1..67fca1f624 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -73,8 +73,8 @@ void software_i2c_attach(unsigned int bus) /* Mux pins to GPIO function for software I2C emulation. */ switch (bus) { case 0: - clrbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - clrbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + clrbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + clrbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_GPIO(IOMUX_I2C1)); @@ -108,8 +108,8 @@ void software_i2c_detach(unsigned int bus) /* Mux pins back to hardware I2C controller. */ switch (bus) { case 0: - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 3223a4ddd4..e0649754b4 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -81,9 +81,9 @@ void tsadc_init(void) { rkclk_configure_tsadc(TSADC_CLOCK_HZ); - setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); + setbits32(&rk3288_tsadc->auto_con, LAST_TSHUT); - setbits_le32(&rk3288_tsadc->int_en, + setbits32(&rk3288_tsadc->int_en, TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 | TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1); @@ -96,7 +96,7 @@ void tsadc_init(void) write32(&rk3288_tsadc->comp2_shut, TSADC_SHUT_VALUE); /* polarity set to high,channel1 for cpu,channel2 for gpu */ - setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | + setbits32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | SRC1_EN | AUTO_EN); /* @@ -104,5 +104,5 @@ void tsadc_init(void) since the tshut polarity defalut low active, so if you enable tsadc iomux,it will output high */ - setbits_le32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); + setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); } diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 5252232f39..f9c49c33d7 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -374,9 +374,9 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) write32(&cru_ptr->dpll_con[3], RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, PLL_FRAC_MODE << PLL_DSMPD_SHIFT)); - clrsetbits_le32(&cru_ptr->dpll_con[2], - PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, - 0 << PLL_FRACDIV_SHIFT); + clrsetbits32(&cru_ptr->dpll_con[2], + PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, + 0 << PLL_FRACDIV_SHIFT); /* * Configure SSC divval. diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 3c6cbe648f..358bb6a7e0 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -60,15 +60,15 @@ u32 get_saradc_value(u32 chn) rkclk_configure_saradc(SARADC_HZ); /* power down adc converter */ - clrbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + clrbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); /* select channel */ - clrsetbits_le32(&rk3399_saradc->ctrl, - ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, - chn << ADC_CHN_SEL_SHIFT); + clrsetbits32(&rk3399_saradc->ctrl, + ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, + chn << ADC_CHN_SEL_SHIFT); /* power up */ - setbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + setbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); udelay(SARADC_DELAY_PU); diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 0e8cda60d7..3fe22f2502 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -120,26 +120,26 @@ static void phy_dll_bypass_set(u32 channel, if (freq <= 125*MHz) { /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - setbits_le32(&denali_phy[86], (0x3 << 2) << 8); - setbits_le32(&denali_phy[214], (0x3 << 2) << 8); - setbits_le32(&denali_phy[342], (0x3 << 2) << 8); - setbits_le32(&denali_phy[470], (0x3 << 2) << 8); + setbits32(&denali_phy[86], (0x3 << 2) << 8); + setbits32(&denali_phy[214], (0x3 << 2) << 8); + setbits32(&denali_phy[342], (0x3 << 2) << 8); + setbits32(&denali_phy[470], (0x3 << 2) << 8); /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - setbits_le32(&denali_phy[547], (0x3 << 2) << 16); - setbits_le32(&denali_phy[675], (0x3 << 2) << 16); - setbits_le32(&denali_phy[803], (0x3 << 2) << 16); + setbits32(&denali_phy[547], (0x3 << 2) << 16); + setbits32(&denali_phy[675], (0x3 << 2) << 16); + setbits32(&denali_phy[803], (0x3 << 2) << 16); } else { /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); + clrbits32(&denali_phy[86], (0x3 << 2) << 8); + clrbits32(&denali_phy[214], (0x3 << 2) << 8); + clrbits32(&denali_phy[342], (0x3 << 2) << 8); + clrbits32(&denali_phy[470], (0x3 << 2) << 8); /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); + clrbits32(&denali_phy[547], (0x3 << 2) << 16); + clrbits32(&denali_phy[675], (0x3 << 2) << 16); + clrbits32(&denali_phy[803], (0x3 << 2) << 16); } } @@ -164,23 +164,23 @@ static void set_memory_map(u32 channel, cs_map = (sdram_ch->rank > 1) ? 3 : 1; reduc = (sdram_ch->bw == 2) ? 0 : 1; - clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); - clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); + clrsetbits32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); + clrsetbits32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); - clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), - cs_map | (reduc << 16)); + clrsetbits32(&denali_ctl[196], 0x3 | (1 << 16), + cs_map | (reduc << 16)); /* PI_199 PI_COL_DIFF:RW:0:4 */ - clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); + clrsetbits32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ - clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); + clrsetbits32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ - clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); + clrsetbits32(&denali_pi[41], 0xf << 24, cs_map << 24); if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3)) write32(&denali_pi[34], 0x2EC7FFFF); } @@ -244,84 +244,84 @@ static void set_ds_odt(u32 channel, reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); - clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); + clrsetbits32(&denali_phy[6], 0xffffff, reg_value); + clrsetbits32(&denali_phy[134], 0xffffff, reg_value); + clrsetbits32(&denali_phy[262], 0xffffff, reg_value); + clrsetbits32(&denali_phy[390], 0xffffff, reg_value); /* * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 * sets termination values for read/idle cycles and drive strength * for write cycles for DQS */ - clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); + clrsetbits32(&denali_phy[7], 0xffffff, reg_value); + clrsetbits32(&denali_phy[135], 0xffffff, reg_value); + clrsetbits32(&denali_phy[263], 0xffffff, reg_value); + clrsetbits32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + clrsetbits32(&denali_phy[544], 0xff, reg_value); + clrsetbits32(&denali_phy[672], 0xff, reg_value); + clrsetbits32(&denali_phy[800], 0xff, reg_value); /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ - clrsetbits_le32(&denali_phy[928], 0xff, reg_value); + clrsetbits32(&denali_phy[928], 0xff, reg_value); /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ - clrsetbits_le32(&denali_phy[937], 0xff, reg_value); + clrsetbits32(&denali_phy[937], 0xff, reg_value); /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ - clrsetbits_le32(&denali_phy[935], 0xff, reg_value); + clrsetbits32(&denali_phy[935], 0xff, reg_value); /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + clrsetbits32(&denali_phy[939], 0xff, reg_value); /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + clrsetbits32(&denali_phy[929], 0xff, reg_value); /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ - clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_n | (tsel_wr_select_p << 4)); - clrsetbits_le32(&denali_phy[925], 0xff, - tsel_rd_select_n | (tsel_rd_select_p << 4)); + clrsetbits32(&denali_phy[924], 0xff, + tsel_wr_select_n | (tsel_wr_select_p << 4)); + clrsetbits32(&denali_phy[925], 0xff, + tsel_rd_select_n | (tsel_rd_select_p << 4)); /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 16; - clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[5], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[133], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[261], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[389], 0x7 << 16, reg_value); /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[6], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[134], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[262], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[390], 0x7 << 24, reg_value); /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ reg_value = tsel_wr_en << 8; - clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[518], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[646], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[774], 0x1 << 8, reg_value); /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ reg_value = tsel_wr_en << 17; - clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[933], 0x1 << 17, reg_value); /* * pad_rst/cke/cs/clk_term tsel 1bits * DENALI_PHY_938/936/940/934 offset_17 */ - clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[938], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[936], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[940], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[934], 0x1 << 17, reg_value); /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ - clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value); } static void phy_io_config(u32 channel, @@ -410,18 +410,18 @@ static void phy_io_config(u32 channel, reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ - clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); + clrsetbits32(&denali_phy[913], 0xfff << 8, reg_value << 8); /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ - clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); + clrsetbits32(&denali_phy[914], 0xfff, reg_value); /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ - clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); + clrsetbits32(&denali_phy[914], 0xfff << 16, reg_value << 16); /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ - clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); + clrsetbits32(&denali_phy[915], 0xfff, reg_value); reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ - clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); + clrsetbits32(&denali_phy[915], 0xfff << 16, reg_value << 16); if (sdram_params->dramtype == LPDDR4) mode_sel = 0x6; @@ -431,21 +431,21 @@ static void phy_io_config(u32 channel, mode_sel = 0x1; /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); + clrsetbits32(&denali_phy[924], 0x7 << 15, mode_sel << 15); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); + clrsetbits32(&denali_phy[926], 0x7 << 6, mode_sel << 6); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); + clrsetbits32(&denali_phy[927], 0x7 << 6, mode_sel << 6); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[928], 0x7 << 14, mode_sel << 14); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[929], 0x7 << 14, mode_sel << 14); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[935], 0x7 << 14, mode_sel << 14); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[937], 0x7 << 14, mode_sel << 14); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14); /* speed setting */ @@ -459,21 +459,21 @@ static void phy_io_config(u32 channel, speed = 0x3; /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); + clrsetbits32(&denali_phy[924], 0x3 << 21, speed << 21); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); + clrsetbits32(&denali_phy[926], 0x3 << 9, speed << 9); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); + clrsetbits32(&denali_phy[927], 0x3 << 9, speed << 9); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[928], 0x3 << 17, speed << 17); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[929], 0x3 << 17, speed << 17); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[935], 0x3 << 17, speed << 17); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[937], 0x3 << 17, speed << 17); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[939], 0x3 << 17, speed << 17); } static int pctl_cfg(u32 channel, @@ -505,13 +505,13 @@ static int pctl_cfg(u32 channel, write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; - clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); + clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); + clrsetbits32(&denali_phy[957], 0x3 << 24, 1 << 24); - setbits_le32(&denali_pi[0], START); - setbits_le32(&denali_ctl[0], START); + setbits32(&denali_pi[0], START); + setbits32(&denali_ctl[0], START); while (1) { tmp = read32(&denali_phy[920]); @@ -539,31 +539,31 @@ static int pctl_cfg(u32 channel, * dqs_tsel_wr_end[7:4] add Half cycle */ tmp = (read32(&denali_phy[84]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[212]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[340]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[468]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 * dq_tsel_wr_end[7:4] add Half cycle */ tmp = (read32(&denali_phy[83]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[211]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[339]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[467]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); phy_io_config(channel, sdram_params); /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); + clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24); /* FIXME: need to care ERROR bit */ stopwatch_init_msecs_expire(&sw, 100); @@ -572,8 +572,8 @@ static int pctl_cfg(u32 channel, return -1; } - clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit); + clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, + pwrup_srefresh_exit); return 0; } @@ -587,10 +587,10 @@ static void select_per_cs_training_index(u32 channel, u32 rank) * PHY_8/136/264/392 * phy_per_cs_training_index_X 1bit offset_24 */ - clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[8], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[136], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[264], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[392], 0x1 << 24, rank << 24); } } @@ -601,26 +601,26 @@ static void override_write_leveling_value(u32 channel) u32 byte; /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - setbits_le32(&denali_phy[896], 1); + setbits32(&denali_phy[896], 1); /* * PHY_8/136/264/392 * phy_per_cs_training_multicast_en_X 1bit offset_16 */ - clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[392], 0x1 << 16, 1 << 16); for (byte = 0; byte < 4; byte++) - clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, + clrsetbits32(&denali_phy[63 + (128 * byte)], 0xffff << 16, 0x200 << 16); /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - clrbits_le32(&denali_phy[896], 1); + clrbits32(&denali_phy[896], 1); /* CTL_200 ctrlupd_req 1bit offset_8 */ - clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); + clrsetbits32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); } static int data_training(u32 channel, @@ -635,7 +635,7 @@ static int data_training(u32 channel, u32 reg_value = 0; /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - setbits_le32(&denali_phy[927], (1 << 22)); + setbits32(&denali_phy[927], (1 << 22)); if (training_flag == PI_FULL_TRAINING) { if (sdram_params->dramtype == LPDDR4) { @@ -657,11 +657,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); + clrsetbits32(&denali_pi[100], 0x3 << 8, 0x2 << 8); /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[92], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); + clrsetbits32(&denali_pi[92], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -690,7 +690,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[100], 0x3 << 8); + clrbits32(&denali_pi[100], 0x3 << 8); } /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ @@ -698,11 +698,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_60 PI_WRLVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); + clrsetbits32(&denali_pi[60], 0x3 << 8, 0x2 << 8); /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[59], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); + clrsetbits32(&denali_pi[59], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -736,7 +736,7 @@ static int data_training(u32 channel, } override_write_leveling_value(channel); - clrbits_le32(&denali_pi[60], 0x3 << 8); + clrbits32(&denali_pi[60], 0x3 << 8); } /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ @@ -758,22 +758,22 @@ static int data_training(u32 channel, * phy_dqs_tsel_enable_X 3bits * DENALI_PHY_6/134/262/390 offset_24 */ - clrbits_le32(&denali_phy[6], 0x7 << 24); - clrbits_le32(&denali_phy[134], 0x7 << 24); - clrbits_le32(&denali_phy[262], 0x7 << 24); - clrbits_le32(&denali_phy[390], 0x7 << 24); + clrbits32(&denali_phy[6], 0x7 << 24); + clrbits32(&denali_phy[134], 0x7 << 24); + clrbits32(&denali_phy[262], 0x7 << 24); + clrbits32(&denali_phy[390], 0x7 << 24); } for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); + clrsetbits32(&denali_pi[80], 0x3 << 24, 0x2 << 24); /* * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 * PI_RDLVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); + clrsetbits32(&denali_pi[74], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -805,7 +805,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[80], 0x3 << 24); + clrbits32(&denali_pi[80], 0x3 << 24); if (sdram_params->dramtype != LPDDR4) { /* @@ -813,10 +813,10 @@ static int data_training(u32 channel, * DENALI_PHY_6/134/262/390 offset_24 */ tmp = reg_value << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[6], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[134], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[262], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[390], 0x7 << 24, tmp); } } @@ -825,11 +825,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); + clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16); /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 8) | (0x3 << 24), - (0x1 << 8) | (i << 24)); + clrsetbits32(&denali_pi[74], + (0x1 << 8) | (0x3 << 24), + (0x1 << 8) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -850,7 +850,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[80], 0x3 << 16); + clrbits32(&denali_pi[80], 0x3 << 16); } /* wdq leveling(LPDDR4 support) */ @@ -861,13 +861,13 @@ static int data_training(u32 channel, * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */ - clrbits_le32(&denali_pi[181], 0x1 << 8); + clrbits32(&denali_pi[181], 0x1 << 8); /* PI_124 PI_WDQLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); + clrsetbits32(&denali_pi[124], 0x3 << 16, 0x2 << 16); /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[121], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); + clrsetbits32(&denali_pi[121], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -882,11 +882,11 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[124], 0x3 << 16); + clrbits32(&denali_pi[124], 0x3 << 16); } /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - clrbits_le32(&denali_phy[927], (1 << 22)); + clrbits32(&denali_phy[927], (1 << 22)); return 0; } @@ -960,8 +960,8 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ if (sdram_params->ch[channel].rank == 1) - setbits_le32(&rk3399_ddr_pctl[channel]->denali_ctl[276], - 1 << 17); + setbits32(&rk3399_ddr_pctl[channel]->denali_ctl[276], + 1 << 17); } write32(&rk3399_pmugrf->os_reg2, sys_reg); @@ -971,7 +971,7 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) write32(&pmucru_ptr->pmucru_rstnhold_con[1], PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | PRESET_GPIO1_HOLD(1)); - clrsetbits_le32(&cru_ptr->glb_rst_con, 0x3, 0x3); + clrsetbits32(&cru_ptr->glb_rst_con, 0x3, 0x3); } static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) @@ -1005,7 +1005,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) for (channel = 0; channel < ch_count; channel++) { denali_phy = rk3399_ddr_publ[channel]->denali_phy; - clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); + clrsetbits32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { printk(BIOS_ERR, "index1 training failed, reset\n"); board_reset(); diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 7ec24648a2..78ce1e366e 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -100,7 +100,7 @@ void tsadc_init(uint32_t polarity) rkclk_configure_tsadc(TSADC_CLOCK_HZ); /* tsadc power sequence */ - clrbits_le32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); + clrbits32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_ON); udelay(50); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_OFF); @@ -125,9 +125,9 @@ void tsadc_init(uint32_t polarity) write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); /* Enable the src0, negative temprature coefficient */ - setbits_le32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); + setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); - setbits_le32(&rk3399_tsadc->auto_con, AUTO_EN); + setbits32(&rk3399_tsadc->auto_con, AUTO_EN); write32(&rk3399_tsadc->comp0_shut, TSADC_SHUT_VALUE); write32(&rk3399_tsadc->int_en, TSHUT_CRU_EN_SRC0 | TSHUT_GPIO_EN_SRC0); diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index e016fbf7c1..434a99ef11 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -54,8 +54,8 @@ static void tcphy_cfg_24m(struct rk3399_tcphy *tcphy) write32(&tcphy->lane[i].tx_rcvdet_st_tmr, 0x30); } - clrsetbits_le32(&tcphy->cmn_diag_hsclk_sel, - TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG); + clrsetbits32(&tcphy->cmn_diag_hsclk_sel, + TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG); } static void tcphy_phy_init(struct rk3399_tcphy *tcphy) @@ -78,11 +78,11 @@ static void tcphy_phy_init(struct rk3399_tcphy *tcphy) static void reset_dwc3(struct rockchip_usb_dwc3 *dwc3) { /* Before Resetting PHY, put Core in Reset */ - setbits_le32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET); + setbits32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET); /* Assert USB3 PHY reset */ - setbits_le32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); + setbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); /* Assert USB2 PHY reset */ - setbits_le32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + setbits32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); } static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) @@ -94,7 +94,7 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) assert(ctl & DWC3_GCTL_CORESOFTRESET); /* Clear USB3 PHY reset (oddly enough, this is really necessary). */ - clrbits_le32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); + clrbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); /* Clear USB2 PHY and core reset. */ usb2phycfg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; -- cgit v1.2.3