From 46514c2b877c29c2d7c2061a9785736e270c0c62 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 11 Jun 2020 11:59:07 -0700 Subject: treewide: Add Kconfig variable MEMLAYOUT_LD_FILE This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/rockchip/rk3288/Kconfig | 4 +++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 35 ------------------------ src/soc/rockchip/rk3288/memlayout.ld | 35 ++++++++++++++++++++++++ src/soc/rockchip/rk3399/Kconfig | 4 +++ src/soc/rockchip/rk3399/include/soc/memlayout.ld | 35 ------------------------ src/soc/rockchip/rk3399/memlayout.ld | 35 ++++++++++++++++++++++++ 6 files changed, 78 insertions(+), 70 deletions(-) delete mode 100644 src/soc/rockchip/rk3288/include/soc/memlayout.ld create mode 100644 src/soc/rockchip/rk3288/memlayout.ld delete mode 100644 src/soc/rockchip/rk3399/include/soc/memlayout.ld create mode 100644 src/soc/rockchip/rk3399/memlayout.ld (limited to 'src/soc/rockchip') diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3198aa4324..3dc9a9b554 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -20,6 +20,10 @@ config SOC_ROCKCHIP_RK3288 if SOC_ROCKCHIP_RK3288 +config MEMLAYOUT_LD_FILE + string + default "src/soc/rockchip/rk3288/memlayout.ld" + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld deleted file mode 100644 index 4ef0163def..0000000000 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, - * so the bootblock loading address must be at 0xFF704004. - */ -SECTIONS -{ - DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) - POSTRAM_CBFS_CACHE(0x01000000, 1M) - DMA_COHERENT(0x10000000, 2M) - FRAMEBUFFER(0x10800000, 8M) - - SRAM_START(0xFF700000) - TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 16K - 4) - PRERAM_CBMEM_CONSOLE(0xFF708000, 2K) - VBOOT2_WORK(0xFF708800, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768) - PRERAM_CBFS_CACHE(0xFF717300, 256) - TIMESTAMP(0xFF717400, 0x180) - STACK(0xFF717580, 3K - 0x180) - SRAM_END(0xFF718000) - - /* 4K of special SRAM in PMU power domain. - * Careful: only supports 32-bit wide write accesses! */ - SYMBOL(pmu_sram, 0xFF720000) - TTB_SUBTABLES(0xFF720800, 1K) - WATCHDOG_TOMBSTONE(0xFF720FFC, 4) - SYMBOL(epmu_sram, 0xFF721000) -} diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld new file mode 100644 index 0000000000..4ef0163def --- /dev/null +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, + * so the bootblock loading address must be at 0xFF704004. + */ +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + DMA_COHERENT(0x10000000, 2M) + FRAMEBUFFER(0x10800000, 8M) + + SRAM_START(0xFF700000) + TTB(0xFF700000, 16K) + BOOTBLOCK(0xFF704004, 16K - 4) + PRERAM_CBMEM_CONSOLE(0xFF708000, 2K) + VBOOT2_WORK(0xFF708800, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768) + PRERAM_CBFS_CACHE(0xFF717300, 256) + TIMESTAMP(0xFF717400, 0x180) + STACK(0xFF717580, 3K - 0x180) + SRAM_END(0xFF718000) + + /* 4K of special SRAM in PMU power domain. + * Careful: only supports 32-bit wide write accesses! */ + SYMBOL(pmu_sram, 0xFF720000) + TTB_SUBTABLES(0xFF720800, 1K) + WATCHDOG_TOMBSTONE(0xFF720FFC, 4) + SYMBOL(epmu_sram, 0xFF721000) +} diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 7e3c44b674..4f7af9e0c2 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -14,6 +14,10 @@ config SOC_ROCKCHIP_RK3399 if SOC_ROCKCHIP_RK3399 +config MEMLAYOUT_LD_FILE + string + default "src/soc/rockchip/rk3399/memlayout.ld" + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld deleted file mode 100644 index 72836b5130..0000000000 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -SECTIONS -{ - DRAM_START(0x00000000) - BL31(0, 0x100000) - POSTRAM_CBFS_CACHE(0x00100000, 8M) - RAMSTAGE(0x00900000, 2M) - DMA_COHERENT(0x10000000, 2M) - - /* 8K of special SRAM in PMU power domain. */ - SYMBOL(pmu_sram, 0xFF3B0000) - WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4) - SYMBOL(epmu_sram, 0xFF3B2000) - - SRAM_START(0xFF8C0000) -#if ENV_RAMSTAGE - REGION(bl31_sram, 0xFF8C0000, 64K, 1) -#else - PRERAM_CBFS_CACHE(0xFF8C0000, 5K) - FMAP_CACHE(0xFF8C1400, 2K) - TIMESTAMP(0xFF8C1C00, 1K) - /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) -#endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) - PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) - STACK(0xFF8ED000, 12K) - SRAM_END(0xFF8F0000) -} diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld new file mode 100644 index 0000000000..72836b5130 --- /dev/null +++ b/src/soc/rockchip/rk3399/memlayout.ld @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +SECTIONS +{ + DRAM_START(0x00000000) + BL31(0, 0x100000) + POSTRAM_CBFS_CACHE(0x00100000, 8M) + RAMSTAGE(0x00900000, 2M) + DMA_COHERENT(0x10000000, 2M) + + /* 8K of special SRAM in PMU power domain. */ + SYMBOL(pmu_sram, 0xFF3B0000) + WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4) + SYMBOL(epmu_sram, 0xFF3B2000) + + SRAM_START(0xFF8C0000) +#if ENV_RAMSTAGE + REGION(bl31_sram, 0xFF8C0000, 64K, 1) +#else + PRERAM_CBFS_CACHE(0xFF8C0000, 5K) + FMAP_CACHE(0xFF8C1400, 2K) + TIMESTAMP(0xFF8C1C00, 1K) + /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) + BOOTBLOCK(0xFF8D8000, 40K) +#endif + VBOOT2_WORK(0XFF8E2000, 12K) + TTB(0xFF8E5000, 24K) + PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) + STACK(0xFF8ED000, 12K) + SRAM_END(0xFF8F0000) +} -- cgit v1.2.3