From 8e6d5f2937c169914e46b5ebc973e5df5e4290a7 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Sun, 30 Aug 2020 13:51:44 +0530
Subject: {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent

Convert 0X -> 0x

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/rockchip/rk3399/clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/rockchip/rk3399')

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index ea1d7ff531..0ba07d6137 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -81,7 +81,7 @@ enum {
 	PLL_SSMOD_RESET_SHIFT		= 2,
 	PLL_SSMOD_DOWNSPEAD_MASK	= 1,
 	PLL_SSMOD_DOWNSPEAD_SHIFT	= 3,
-	PLL_SSMOD_DIVVAL_MASK		= 0Xf,
+	PLL_SSMOD_DIVVAL_MASK		= 0xf,
 	PLL_SSMOD_DIVVAL_SHIFT		= 4,
 	PLL_SSMOD_SPREADAMP_MASK	= 0x1f,
 	PLL_SSMOD_SPREADAMP_SHIFT	= 8,
-- 
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