From 3d703bcc70c346ba1edad1b8f8391e62814f3ceb Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Tue, 28 Jun 2016 14:19:18 +0800 Subject: rockchip/rk3399: Use apll instead of apll_l define Use the apll define instead of the apll_l define so it can be reused when setting apll_b. BRANCH=None BUG=None TEST=Boot from Gru Change-Id: Iebc4ce3b66a86c33653292340b9855265ac4fc07 Signed-off-by: Martin Roth Original-Commit-Id: eb578110d19a35ef04f8749fdc202055abd50fd1 Original-Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4 Original-Signed-off-by: Lin Huang Original-Reviewed-on: https://chromium-review.googlesource.com/356398 Original-Reviewed-by: Douglas Anderson Original-Tested-by: Douglas Anderson Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Douglas Anderson Reviewed-on: https://review.coreboot.org/15582 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/rockchip/rk3399/bootblock.c | 2 +- src/soc/rockchip/rk3399/clock.c | 16 ++++++++-------- src/soc/rockchip/rk3399/include/soc/clock.h | 8 ++++---- 3 files changed, 13 insertions(+), 13 deletions(-) (limited to 'src/soc/rockchip/rk3399') diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index 4f3d57c502..3e95a17267 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -22,7 +22,7 @@ void bootblock_soc_init(void) { rkclk_init(); - rkclk_configure_cpu(APLL_L_600_MHZ); + rkclk_configure_cpu(APLL_600_MHZ); /* all ddr range non-secure */ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 8b274542c5..9388487672 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -47,12 +47,12 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); -static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); -static const struct pll_div *apll_l_cfgs[] = { - [APLL_L_1600_MHZ] = &apll_l_1600_cfg, - [APLL_L_600_MHZ] = &apll_l_600_cfg, +static const struct pll_div *apll_cfgs[] = { + [APLL_1600_MHZ] = &apll_1600_cfg, + [APLL_600_MHZ] = &apll_600_cfg, }; enum { @@ -487,16 +487,16 @@ void rkclk_init(void) HCLK_PERILP1_PLL_SEL_SHIFT)); } -void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq) +void rkclk_configure_cpu(enum apll_frequencies apll_l_freq) { u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; u32 apll_l_hz; - apll_l_hz = apll_l_cfgs[apll_l_freq]->freq; + apll_l_hz = apll_cfgs[apll_l_freq]->freq; - rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]); + rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_cfgs[apll_l_freq]); aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 6781b5c691..70b819a374 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -96,14 +96,14 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PWM_CLOCK_HZ PMU_PCLK_HZ -enum apll_l_frequencies { - APLL_L_1600_MHZ, - APLL_L_600_MHZ, +enum apll_frequencies { + APLL_1600_MHZ, + APLL_600_MHZ, }; void rkclk_init(void); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); -void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq); +void rkclk_configure_cpu(enum apll_frequencies apll_l_freq); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_emmc(void); void rkclk_configure_i2s(unsigned int hz); -- cgit v1.2.3