From ecd600a0caa18b0346e4b8024aae2263db0d7821 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Thu, 16 Nov 2017 09:52:27 +0800 Subject: rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide Accroding to datasheet, feedback divider register high value is only 4 bit, it currently uses 5 bit, so correct it. Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e Signed-off-by: Lin Huang Reviewed-on: https://review.coreboot.org/22478 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/rockchip/rk3399/include/soc/mipi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/rockchip/rk3399/include') diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index 2dfbc521d2..bccaf287d3 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -197,7 +197,7 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8); #define LOW_PROGRAM_EN 0 #define HIGH_PROGRAM_EN BIT(7) #define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f) -#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f) +#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0xf) #define PLL_LOOP_DIV_EN BIT(5) #define PLL_INPUT_DIV_EN BIT(4) -- cgit v1.2.3