From c7f32a5bb444de3de22904cad1fac0f08b88ee8d Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Wed, 4 May 2016 15:54:37 +0800 Subject: rockchip: rk3399: add routines to set vop clocks Let vop aclk sources from CPLL, and vop dclk from NPLL. The dclk freq is decided by the edid mode pixel_clock which may require high accuracy like 252750KHz. The pll_para_config() can calculate the dividers for PLL to output desired clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=check display with the other patches Change-Id: I12cf27d3d1177a8b1c4cfbd7c0be10204e3d3142 Signed-off-by: Martin Roth Original-Commit-Id: 0f019b055fffebe9ea3928aae1e25b0ad4feef81 Original-Change-Id: Icef58f87041905961772b69c6b8170d5a866a531 Original-Signed-off-by: Lin Huang Original-Signed-off-by: Shunqian Zheng Original-Reviewed-on: https://chromium-review.googlesource.com/342335 Original-Tested-by: Vadim Bendebury Original-Reviewed-by: Vadim Bendebury Reviewed-on: https://review.coreboot.org/14846 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury --- src/soc/rockchip/rk3399/include/soc/clock.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/rockchip/rk3399/include') diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 4e96e997a8..65e2e74a57 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -103,10 +103,12 @@ enum apll_l_frequencies { }; void rkclk_init(void); +int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_saradc(unsigned int hz); void rkclk_configure_spi(unsigned int bus, unsigned int hz); +void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); uint32_t rkclk_i2c_clock_for_bus(unsigned bus); -- cgit v1.2.3