From ba2b63a20abf3e5955cce43128911f90609beac1 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Mon, 25 Jul 2016 10:06:09 +0800 Subject: rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevin We should be running faster. Faster = better. BRANCH=None BUG=chrome-os-partner:54873 TEST=Boot; stressapptest -M 1028 -s 10000 Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8 Signed-off-by: Martin Roth Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20 Original-Signed-off-by: Lin Huang Original-Reviewed-on: https://chromium-review.googlesource.com/362822 Original-Reviewed-by: Douglas Anderson Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/16241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/soc/rockchip/rk3399/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/rockchip/rk3399/clock.c') diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index cfe363c681..ed9afda3ca 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -556,9 +556,9 @@ void rkclk_configure_ddr(unsigned int hz) dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; break; - case 928*MHz: + case 933*MHz: dpll_cfg = (struct pll_div) - {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; + {.refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}; break; default: die("Unsupported SDRAM frequency, add to clock.c!"); -- cgit v1.2.3