From 8d1b0f1dbd2736391d4011106527a1e5b286307d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 20 Feb 2020 18:20:57 +0100 Subject: soc/rockchip: Fix typos Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39028 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/rockchip/rk3399/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/rockchip/rk3399/clock.c') diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 4cd2839547..d2f5b7c6d1 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -304,7 +304,7 @@ static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " - "postdiv2=%d, vco=%u khz, output=%u khz\n", + "postdiv2=%d, vco=%u kHz, output=%u kHz\n", pll_con, div->fbdiv, div->refdiv, div->postdiv1, div->postdiv2, vco_khz, output_khz); assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && @@ -485,7 +485,7 @@ void rkclk_init(void) /* some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. - * Please consider these threee lines as a fix of bootrom bug. + * Please consider these three lines as a fix of bootrom bug. */ write32(&cru_ptr->clksel_con[12], 0xffff4101); write32(&cru_ptr->clksel_con[19], 0xffff033f); -- cgit v1.2.3