From 9ed93cb5d50f94f9c43db2eb29764cd6302b4bb0 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Sun, 22 May 2016 16:09:54 -0700 Subject: gru: kevin: configure board GPIOs Set board GPIOs as required and add their description into the appropriate section of the coreboot table, to make them available to depthcharge. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to use keyboard on Gru, which indicates that the EC interrupt GPIO is properly configured. The rest of the pins will be verified later. Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727 Signed-off-by: Martin Roth Original-Commit-Id: e02a05f Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/346631 Reviewed-on: https://review.coreboot.org/15031 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/rockchip/rk3399/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/rockchip/rk3399/Makefile.inc') diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 8abafe362b..77958d577f 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -47,6 +47,8 @@ romstage-y += ../common/pwm.c romstage-y += timer.c romstage-y += romstage.c romstage-y += tsadc.c +romstage-y += gpio.c +romstage-y += ../common/gpio.c ################################################################################ -- cgit v1.2.3