From 6b0d0851645cf369e2fd08a2d11ffc441df7f7aa Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 8 Jun 2022 10:23:32 +0800 Subject: security/vboot: Deprecate VBOOT_VBNV_EC Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all ChromeOS devices and they've reached the end of life since Feb 2022. Therefore, remove VBOOT_VBNV_EC for them, each with different replacement. - nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. - veyron: Add RW_NVRAM to their FMAP (by reducing the size of SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its allotted size. - daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. - peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC option. Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for vboot nvdata (VBNV). Also add a check in read_vbnv() and save_vbnv() for VBNV options. BUG=b:178689388 TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a TEST=util/abuild/abuild -t GOOGLE_DAISY -a TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a BRANCH=none Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/rockchip/rk3288/memlayout.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/rockchip/rk3288') diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 32962257b2..5e35a064b9 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -18,9 +18,9 @@ SECTIONS SRAM_START(0xFF700000) TTB(0xFF700000, 16K) BOOTBLOCK(0xFF704004, 16K - 4) - PRERAM_CBMEM_CONSOLE(0xFF708000, 2K) - VBOOT2_WORK(0xFF708800, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768) + PRERAM_CBMEM_CONSOLE(0xFF708000, 1K) + VBOOT2_WORK(0xFF708400, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B400, 47K + 768) PRERAM_CBFS_CACHE(0xFF717300, 256) TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) -- cgit v1.2.3