From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/rockchip/rk3288/hdmi.c | 92 ++++++++++++++-------------- src/soc/rockchip/rk3288/sdram.c | 108 ++++++++++++++++----------------- src/soc/rockchip/rk3288/software_i2c.c | 8 +-- src/soc/rockchip/rk3288/tsadc.c | 8 +-- 4 files changed, 108 insertions(+), 108 deletions(-) (limited to 'src/soc/rockchip/rk3288') diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index b4de270fc5..6569d295ea 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -250,8 +250,8 @@ static void hdmi_update_csc_coeffs(void) } } - clrsetbits_le32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, - csc_scale); + clrsetbits32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, + csc_scale); } static void hdmi_video_csc(void) @@ -261,8 +261,8 @@ static void hdmi_video_csc(void) /* configure the csc registers */ write32(&hdmi_regs->csc_cfg, interpolation); - clrsetbits_le32(&hdmi_regs->csc_scale, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); + clrsetbits32(&hdmi_regs->csc_scale, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); hdmi_update_csc_coeffs(); } @@ -281,18 +281,18 @@ static void hdmi_video_packetize(void) HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); write32(&hdmi_regs->vp_pr_cd, val); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); /* data from pixel repeater block */ vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | - HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | + HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, - 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, + 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); write32(&hdmi_regs->vp_remap, remap_size); @@ -300,23 +300,23 @@ static void hdmi_video_packetize(void) HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_DISABLE; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | - HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, - vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | + HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, + vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | - HDMI_VP_STUFF_YCC422_STUFFING_MASK, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | + HDMI_VP_STUFF_YCC422_STUFFING_MASK, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, - output_select); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, + output_select); } static inline void hdmi_phy_test_clear(u8 bit) { - clrsetbits_le32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, - bit << HDMI_PHY_TST0_TSTCLR_OFFSET); + clrsetbits32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, + bit << HDMI_PHY_TST0_TSTCLR_OFFSET); } static int hdmi_phy_wait_i2c_done(u32 msec) @@ -352,46 +352,46 @@ static void hdmi_phy_i2c_write(u16 data, u8 addr) static void hdmi_phy_enable_power(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, - enable << HDMI_PHY_CONF0_PDZ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, + enable << HDMI_PHY_CONF0_PDZ_OFFSET); } static void hdmi_phy_enable_tmds(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, - enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, + enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); } static void hdmi_phy_enable_spare(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, - enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, + enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); } static void hdmi_phy_gen2_pddq(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, - enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, + enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); } static void hdmi_phy_gen2_txpwron(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, - enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, + enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); } static void hdmi_phy_sel_data_en_pol(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_SELDATAENPOL_MASK, - enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_SELDATAENPOL_MASK, + enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); } static void hdmi_phy_sel_interface_control(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, - enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, + enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); } static int hdmi_phy_configure(u32 mpixelclock) @@ -723,8 +723,8 @@ static int hdmi_ddc_wait_i2c_done(int msec) static void hdmi_ddc_reset(void) { - clrsetbits_le32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, - HDMI_I2CM_SOFTRSTZ); + clrsetbits32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, + HDMI_I2CM_SOFTRSTZ); } static int hdmi_read_edid(int block, u8 *buff) @@ -737,7 +737,7 @@ static int hdmi_read_edid(int block, u8 *buff) /* set ddc i2c clk which devided from ddc_clk to 100khz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); - clrsetbits_le32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, + clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV_STD_MODE); write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR); @@ -751,13 +751,13 @@ static int hdmi_read_edid(int block, u8 *buff) write32(&hdmi_regs->i2cmess, shift + 8 * n); if (block == 0) - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8, - HDMI_I2CM_OPT_RD8); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8, + HDMI_I2CM_OPT_RD8); else - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8_EXT, - HDMI_I2CM_OPT_RD8_EXT); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8_EXT, + HDMI_I2CM_OPT_RD8_EXT); if (hdmi_ddc_wait_i2c_done(10)) { hdmi_ddc_reset(); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 74038b078e..3305263458 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -522,14 +522,14 @@ static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; rkclk_ddr_reset(channel, 1, 1); udelay(1); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); rkclk_ddr_reset(channel, 1, 0); @@ -544,23 +544,23 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; if (freq <= 250*MHz) { if (freq <= 150*MHz) - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); else - setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + setbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + setbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } else { - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + clrbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } } @@ -637,7 +637,7 @@ static void pctl_cfg(u32 channel, break; } - setbits_le32(&ddr_pctl_regs->scfg, 1); + setbits32(&ddr_pctl_regs->scfg, 1); } static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) @@ -668,33 +668,33 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) switch (sdram_params->dramtype) { case LPDDR3: - clrsetbits_le32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) + clrsetbits32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) | PGCR_DFTCMP(0) | PGCR_DQSCFG(1) | PGCR_ITMDMD(0)); /* DDRMODE select LPDDR3 */ - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_LPDDR2_LPDDR3)); - clrsetbits_le32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, + clrsetbits32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, DQSRES_CFG(4) | DQSNRES_CFG(0xc)); i = TDQSCKMAX_VAL(read32(&ddr_publ_regs->dtpr[1])) - TDQSCK_VAL(read32(&ddr_publ_regs->dtpr[1])); - clrsetbits_le32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, + clrsetbits32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, DQSGE_CFG(i) | DQSGX_CFG(i)); break; case DDR3: - clrbits_le32(&ddr_publ_regs->pgcr, 0x1f); - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrbits32(&ddr_publ_regs->pgcr, 0x1f); + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_DDR3)); break; } if (sdram_params->odt) { /*dynamic RTT enable */ for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + setbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } else { /*dynamic RTT disable */ for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + clrbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } @@ -702,7 +702,7 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs) { - setbits_le32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST + setbits32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & @@ -723,10 +723,10 @@ static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank, static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs, u32 dramtype) { - setbits_le32(&ddr_publ_regs->pir, - (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP - | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC - | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + setbits32(&ddr_publ_regs->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) != (PGSR_IDONE | PGSR_DLDONE)) @@ -775,42 +775,42 @@ static void set_bandwidth_ratio(u32 channel, u32 n) struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; if (n == 1) { - setbits_le32(&ddr_pctl_regs->ppcfg, 1); + setbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_SETBITS(1 << (8 + channel))); - setbits_le32(&msch_regs->ddrtiming, 1 << 31); + setbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte disable*/ - clrbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - clrbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*disable DLL */ - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); } else { - clrbits_le32(&ddr_pctl_regs->ppcfg, 1); + clrbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << (8 + channel))); - clrbits_le32(&msch_regs->ddrtiming, 1 << 31); + clrbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte enable*/ - setbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - setbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*enable DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); /* reset DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); } - setbits_le32(&ddr_pctl_regs->dfistcfg0, 1 << 2); + setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2); } @@ -829,19 +829,19 @@ static int data_training(u32 channel, write32(&ddr_pctl_regs->trefi, 0); if (sdram_params->dramtype != LPDDR3) - setbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + setbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); rank = sdram_params->ch[channel].rank | 1; for (j = 0; j < ARRAY_SIZE(step); j++) { /* * trigger QSTRN and RVTRN * clear DTDONE status */ - setbits_le32(&ddr_publ_regs->pir, PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, PIR_CLRSR); /* trigger DTT */ - setbits_le32(&ddr_publ_regs->pir, - PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | - PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); udelay(1); /* wait echo byte DTDONE */ while ((read32(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank) @@ -869,7 +869,7 @@ static int data_training(u32 channel, send_command(ddr_pctl_regs, rank, REF_CMD, 0); if (sdram_params->dramtype != LPDDR3) - clrbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + clrbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); /* resume auto refresh */ write32(&ddr_pctl_regs->trefi, sdram_params->pctl_timing.trefi); @@ -928,9 +928,9 @@ static void dram_cfg_rbc(u32 chnum, struct rk3288_msch_regs *msch_regs = rk3288_msch[chnum]; if (sdram_params->ch[chnum].bk == 3) - clrsetbits_le32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); + clrsetbits32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); else - clrbits_le32(&ddr_publ_regs->dcr, PDQ_MSK); + clrbits32(&ddr_publ_regs->dcr, PDQ_MSK); write32(&msch_regs->ddrconf, sdram_params->ddrconfig); } @@ -1029,8 +1029,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) * CS1, n=2 * CS0 & CS1, n = 3 */ - clrsetbits_le32(&ddr_publ_regs->pgcr, 0xF << 18, - (sdram_params->ch[channel].rank | 1) << 18); + clrsetbits32(&ddr_publ_regs->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); /* DS=40ohm,ODT=155ohm */ zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2) | PU_OUTPUT(0x19) | PD_OUTPUT(0x19); diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index 8c439842c1..67fca1f624 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -73,8 +73,8 @@ void software_i2c_attach(unsigned int bus) /* Mux pins to GPIO function for software I2C emulation. */ switch (bus) { case 0: - clrbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - clrbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + clrbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + clrbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_GPIO(IOMUX_I2C1)); @@ -108,8 +108,8 @@ void software_i2c_detach(unsigned int bus) /* Mux pins back to hardware I2C controller. */ switch (bus) { case 0: - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 3223a4ddd4..e0649754b4 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -81,9 +81,9 @@ void tsadc_init(void) { rkclk_configure_tsadc(TSADC_CLOCK_HZ); - setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); + setbits32(&rk3288_tsadc->auto_con, LAST_TSHUT); - setbits_le32(&rk3288_tsadc->int_en, + setbits32(&rk3288_tsadc->int_en, TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 | TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1); @@ -96,7 +96,7 @@ void tsadc_init(void) write32(&rk3288_tsadc->comp2_shut, TSADC_SHUT_VALUE); /* polarity set to high,channel1 for cpu,channel2 for gpu */ - setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | + setbits32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | SRC1_EN | AUTO_EN); /* @@ -104,5 +104,5 @@ void tsadc_init(void) since the tshut polarity defalut low active, so if you enable tsadc iomux,it will output high */ - setbits_le32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); + setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); } -- cgit v1.2.3