From 82ba4d092b729d0063a22d445f315d08ad7a3e07 Mon Sep 17 00:00:00 2001
From: huang lin <hl@rock-chips.com>
Date: Sat, 16 Aug 2014 10:49:32 +0800
Subject: rk3288: add cpu and chip

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I4c1864171e56a81e8eda95a15ca6a6bc1adc7a70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 814af4b653432295cb6d7222af4a6e5a8d9dfbf6
Original-Change-Id: I1a986fbc8b3737bae655207dd89865dd39aecf87
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209467
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/8866
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
---
 src/soc/rockchip/rk3288/soc.c | 63 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 src/soc/rockchip/rk3288/soc.c

(limited to 'src/soc/rockchip/rk3288/soc.c')

diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
new file mode 100644
index 0000000000..0985c0843f
--- /dev/null
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <delay.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+#include <arch/cache.h>
+#include <soc/rockchip/rk3288/gpio.h>
+#include "soc.h"
+#include "chip.h"
+
+static void soc_enable(device_t dev)
+{
+	ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
+}
+
+static void soc_init(device_t dev)
+{
+
+}
+
+static void soc_noop(device_t dev)
+{
+
+}
+
+static struct device_operations soc_ops = {
+	.read_resources   = soc_noop,
+	.set_resources    = soc_noop,
+	.enable_resources = soc_enable,
+	.init             = soc_init,
+	.scan_bus         = 0,
+};
+
+static void enable_rk3288_dev(device_t dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_rockchip_rk3288_ops = {
+	CHIP_NAME("SOC Rockchip 3288")
+	.enable_dev = enable_rk3288_dev,
+};
-- 
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