From 46514c2b877c29c2d7c2061a9785736e270c0c62 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 11 Jun 2020 11:59:07 -0700 Subject: treewide: Add Kconfig variable MEMLAYOUT_LD_FILE This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/rockchip/rk3288/memlayout.ld | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 src/soc/rockchip/rk3288/memlayout.ld (limited to 'src/soc/rockchip/rk3288/memlayout.ld') diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld new file mode 100644 index 0000000000..4ef0163def --- /dev/null +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, + * so the bootblock loading address must be at 0xFF704004. + */ +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + DMA_COHERENT(0x10000000, 2M) + FRAMEBUFFER(0x10800000, 8M) + + SRAM_START(0xFF700000) + TTB(0xFF700000, 16K) + BOOTBLOCK(0xFF704004, 16K - 4) + PRERAM_CBMEM_CONSOLE(0xFF708000, 2K) + VBOOT2_WORK(0xFF708800, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768) + PRERAM_CBFS_CACHE(0xFF717300, 256) + TIMESTAMP(0xFF717400, 0x180) + STACK(0xFF717580, 3K - 0x180) + SRAM_END(0xFF718000) + + /* 4K of special SRAM in PMU power domain. + * Careful: only supports 32-bit wide write accesses! */ + SYMBOL(pmu_sram, 0xFF720000) + TTB_SUBTABLES(0xFF720800, 1K) + WATCHDOG_TOMBSTONE(0xFF720FFC, 4) + SYMBOL(epmu_sram, 0xFF721000) +} -- cgit v1.2.3