From 42f15054b178efe9a4d1c8a4e0c203d1aa4aad01 Mon Sep 17 00:00:00 2001
From: Patrick Georgi <patrick@coreboot.org>
Date: Sat, 7 Oct 2023 11:16:43 +0200
Subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This is in preparation of a larger heap. I went for 2MB because why not?

Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/soc/rockchip/rk3288/memlayout.ld | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/rockchip/rk3288/memlayout.ld')

diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld
index 5e35a064b9..ea69a42704 100644
--- a/src/soc/rockchip/rk3288/memlayout.ld
+++ b/src/soc/rockchip/rk3288/memlayout.ld
@@ -10,7 +10,7 @@
 SECTIONS
 {
 	DRAM_START(0x00000000)
-	RAMSTAGE(0x00200000, 128K)
+	RAMSTAGE(0x00200000, 2M)
 	POSTRAM_CBFS_CACHE(0x01000000, 1M)
 	DMA_COHERENT(0x10000000, 2M)
 	FRAMEBUFFER(0x10800000, 8M)
-- 
cgit v1.2.3