From cdf92eacd5d2f85de473778cc1ebf35c2468a7f2 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 9 Dec 2014 12:18:00 -0800 Subject: rk3288: Disable ramstage compression by default The ramstage is loaded from romstage, so the LZMA scratchpad buffer used to decompress it is part of the romstage BSS in SRAM. On RK3288, SRAM cannot be cached which makes the decompression so slow that it's faster to just load an uncompressed image from SPI. Disable ramstage compression on this SoC to account for that. [pg: implementation avoids restructuring all of Kconfig] BRANCH=None BUG=None TEST=Built for Pinky and Falco, confirmed that the former didn't have COMPRESS_RAMSTAGE in its .config and the latter still did. Measured a speed-up of about 35ms on Pinky. (For some weird reason, the decompression of the payload also takes way longer than on other platforms, although not as long as the ramstage. I have no explanation for that and can't really think of a good way to figure it out... maybe the Cortex-A12 is just terrible at some operation that LZMA uses a lot?) Change-Id: I9f67f7537696ec09496483b16b59a8b73f4cb11b Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/234192 Reviewed-by: Aaron Durbin Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/9792 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/soc/rockchip/rk3288/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/rockchip/rk3288/Kconfig') diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 48ea7fc5d5..60d69f678f 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,6 +30,7 @@ config SOC_ROCKCHIP_RK3288 select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE + select UNCOMPRESSED_RAMSTAGE if SOC_ROCKCHIP_RK3288 -- cgit v1.2.3