From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/rockchip/common/edp.c | 26 +++++++++++++------------- src/soc/rockchip/common/gpio.c | 26 +++++++++++++------------- src/soc/rockchip/common/pwm.c | 2 +- src/soc/rockchip/common/spi.c | 14 +++++++------- src/soc/rockchip/common/vop.c | 38 +++++++++++++++++++------------------- 5 files changed, 53 insertions(+), 53 deletions(-) (limited to 'src/soc/rockchip/common') diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index ea0930a058..18afc3a50a 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -97,7 +97,7 @@ static void rk_edp_init_interrupt(struct rk_edp *edp) static void rk_edp_enable_sw_function(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, SW_FUNC_EN_N); + clrbits32(&edp->regs->func_en_1, SW_FUNC_EN_N); } static int rk_edp_get_pll_lock_status(struct rk_edp *edp) @@ -116,7 +116,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG); - clrbits_le32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); + clrbits32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -128,7 +128,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | + clrbits32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N | SSC_FUNC_EN_N); } @@ -139,20 +139,20 @@ static void rk_edp_init_aux(struct rk_edp *edp) write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ - setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + setbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1)); /* Enable AUX channel module */ - clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + clrbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); } static int rk_edp_aux_enable(struct rk_edp *edp) { struct stopwatch sw; - setbits_le32(&edp->regs->aux_ch_ctl_2, AUX_EN); + setbits32(&edp->regs->aux_ch_ctl_2, AUX_EN); stopwatch_init_msecs_expire(&sw, 20); do { if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN)) @@ -698,7 +698,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, write32(&edp->regs->buf_data_ctl, val); /* Set normal AUX CH command */ - clrbits_le32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); + clrbits32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); /* * If Rx sends defer, Tx sends only reads @@ -816,7 +816,7 @@ static void rk_edp_init_video(struct rk_edp *edp) static void rk_edp_config_video_slave_mode(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, + clrbits32(&edp->regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); } @@ -828,7 +828,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, u32 val; if (type == REGISTER_M) { - setbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + setbits32(&edp->regs->sys_ctl_4, FIX_M_VID); val = m_value & 0xff; write32(&edp->regs->m_vid_0, val); val = (m_value >> 8) & 0xff; @@ -843,7 +843,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, val = (n_value >> 16) & 0xff; write32(&edp->regs->n_vid_2, val); } else { - clrbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + clrbits32(&edp->regs->sys_ctl_4, FIX_M_VID); write32(&edp->regs->n_vid_0, 0x00); write32(&edp->regs->n_vid_1, 0x80); @@ -914,10 +914,10 @@ static int rk_edp_config_video(struct rk_edp *edp) rk_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0); /* For video bist, Video timing must be generated by register */ - clrbits_le32(&edp->regs->video_ctl_10, F_SEL); + clrbits32(&edp->regs->video_ctl_10, F_SEL); /* Disable video mute */ - clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); + clrbits32(&edp->regs->video_ctl_1, VIDEO_MUTE); return 0; } @@ -1000,7 +1000,7 @@ int rk_edp_prepare(void) int rk_edp_enable(void) { /* Enable video at next frame */ - setbits_le32(&rk_edp.regs->video_ctl_1, VIDEO_EN); + setbits32(&rk_edp.regs->video_ctl_1, VIDEO_EN); return rk_edp_is_video_stream_on(&rk_edp); } diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 3d7e1614e0..16ab385b03 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -24,16 +24,16 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr, - 1 << gpio.num, dir << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_ddr, + 1 << gpio.num, dir << gpio.num); } static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288)) - clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), - pull_val << (gpio.idx * 2)); + clrsetbits32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), + pull_val << (gpio.idx * 2)); else write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), pull_val << (gpio.idx * 2))); @@ -83,13 +83,13 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull) case IRQ_TYPE_LEVEL_LOW: break; } - clrsetbits_le32(&gpio_port[gpio.port]->int_polarity, - mask, int_polarity); - clrsetbits_le32(&gpio_port[gpio.port]->inttype_level, - mask, inttype_level); + clrsetbits32(&gpio_port[gpio.port]->int_polarity, + mask, int_polarity); + clrsetbits32(&gpio_port[gpio.port]->inttype_level, + mask, inttype_level); - setbits_le32(&gpio_port[gpio.port]->inten, mask); - clrbits_le32(&gpio_port[gpio.port]->intmask, mask); + setbits32(&gpio_port[gpio.port]->inten, mask); + clrbits32(&gpio_port[gpio.port]->intmask, mask); } int gpio_irq_status(gpio_t gpio) @@ -100,7 +100,7 @@ int gpio_irq_status(gpio_t gpio) if (!(int_status & mask)) return 0; - setbits_le32(&gpio_port[gpio.port]->porta_eoi, mask); + setbits32(&gpio_port[gpio.port]->porta_eoi, mask); return 1; } @@ -111,8 +111,8 @@ int gpio_get(gpio_t gpio) void gpio_set(gpio_t gpio, int value) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, - !!value << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, + !!value << gpio.num); } void gpio_output(gpio_t gpio, int value) diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index e5da05e672..82fc2596c0 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -79,5 +79,5 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) write32(&rk_pwm->pwm[id].pwm_period_hpr, period); write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty); - setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); + setbits32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); } diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 0307e24d35..d91bae0eac 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -70,13 +70,13 @@ static struct rockchip_spi_slave *to_rockchip_spi(const struct spi_slave *slave) static void spi_cs_activate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - setbits_le32(®s->ser, 1); + setbits32(®s->ser, 1); } static void spi_cs_deactivate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - clrbits_le32(®s->ser, 1); + clrbits32(®s->ser, 1); } static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) @@ -141,8 +141,8 @@ void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) /* Rxd Sample Delay */ rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); assert(rsd <= 3); - clrsetbits_le32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, - rsd << SPI_RXDSD_OFFSET); + clrsetbits32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, + rsd << SPI_RXDSD_OFFSET); } static int spi_ctrlr_claim_bus(const struct spi_slave *slave) @@ -172,7 +172,7 @@ static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) { - clrsetbits_le32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, + clrsetbits32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, tmod << SPI_TMOD_OFFSET); } @@ -275,9 +275,9 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } mask = SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET; if (use_16bit) - clrbits_le32(®s->ctrlr0, mask); + clrbits32(®s->ctrlr0, mask); else - setbits_le32(®s->ctrlr0, mask); + setbits32(®s->ctrlr0, mask); /* Enable/disable transmitter and receiver as needed to * avoid sending or reading spurious bits. */ diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 9c70b78171..6e0ce4086c 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -60,7 +60,7 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1)); - clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, + clrsetbits32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); @@ -89,10 +89,10 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) else lb_mode = LB_RGB_1280X8; - clrsetbits_le32(&preg->win0_ctrl0, - M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, - V_WIN0_LB_MODE(lb_mode) | - V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); + clrsetbits32(&preg->win0_ctrl0, + M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, + V_WIN0_LB_MODE(lb_mode) | + V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); } void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) @@ -111,34 +111,34 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) switch (mode) { case VOP_MODE_HDMI: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); dsp_out_mode = 15; break; case VOP_MODE_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_DUAL_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_EDP: default: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_EDP_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_EDP_OUT_EN(1)); dsp_out_mode = 15; break; } - clrsetbits_le32(&preg->dsp_ctrl0, - M_DSP_OUT_MODE | M_DSP_VSYNC_POL | - M_DSP_HSYNC_POL, - V_DSP_OUT_MODE(dsp_out_mode) | - V_DSP_HSYNC_POL(edid->mode.phsync == '+') | - V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); + clrsetbits32(&preg->dsp_ctrl0, + M_DSP_OUT_MODE | M_DSP_VSYNC_POL | + M_DSP_HSYNC_POL, + V_DSP_OUT_MODE(dsp_out_mode) | + V_DSP_HSYNC_POL(edid->mode.phsync == '+') | + V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); -- cgit v1.2.3