From 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 Aug 2018 18:55:58 +0200 Subject: src: Fix typo Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/rockchip/common/include/soc/spi.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/rockchip/common') diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index 0e1847c985..ce5de83c62 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -101,9 +101,9 @@ check_member(rockchip_spi, rxdr, 0x800); /* SSN to Sclk_out delay */ #define SPI_SSN_DELAY_OFFSET 10 #define SPI_SSN_DELAY_MASK 0x1 -/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ +/* the period between ss_n active and sclk_out active is half sclk_out cycles */ #define SPI_SSN_DELAY_HALF 0x00 -/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ +/* the period between ss_n active and sclk_out active is one sclk_out cycle */ #define SPI_SSN_DELAY_ONE 0x01 /* Serial Endian Mode */ -- cgit v1.2.3