From bd0b51c0be1ec2c9a5f02de3c13108c13941e2c2 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Thu, 21 Mar 2019 14:20:52 -0700 Subject: sdm845: Add QCLib to RomStage to perform IP init CB acts as I/O handler for QCLib (e.g. DDR training data) This interface allows bi-directional data flow between CB and QCLib Tested and working interfaces: DDR Training data QCLib serial console output DDR Information (base & size) limits cfg data TEST=build & run Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Signed-off-by: T Michael Turney Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sdm845/include/soc/memlayout.ld | 21 +++++++++++++-------- src/soc/qualcomm/sdm845/include/soc/mmu.h | 2 -- src/soc/qualcomm/sdm845/include/soc/symbols.h | 4 +++- 3 files changed, 16 insertions(+), 11 deletions(-) (limited to 'src/soc/qualcomm/sdm845/include') diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index 7063c6910e..b1b633317f 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -28,11 +28,12 @@ SECTIONS { SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - DMA_COHERENT(0x14699000, 0x2000) + DMA_COHERENT(0x14699000, 8K) + REGION(qcsdi, 0x146AC000, 44K, 4K) SSRAM_END(0x146C0000) BSRAM_START(0x14800000) - REGION(fw_reserved2, 0x14800000, 0x16000, 4096) + REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) BOOTBLOCK(0x14816000, 40K) TTB(0x14820000, 56K) VBOOT2_WORK(0x1482E000, 12K) @@ -40,15 +41,19 @@ SECTIONS TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) - REGION(bsram_unused, 0x1484FC00, 0xA2400, 0x100) - REGION(qclib, 0x148F2000, 0x80000, 4096) - REGION(dcb, 0x14972000, 0x4000, 4096) - REGION(pmic, 0x14976000, 0xA000, 4096) + REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100) + REGION(ddr_information, 0x148EDF00, 256, 256) + REGION(limits_cfg, 0x148EE000, 4K, 4K) + REGION(qclib_serial_log, 0x148EF000, 4K, 4K) + REGION(ddr_training, 0x148F0000, 8K, 4K) + REGION(qclib, 0x148F2000, 512K, 4K) + REGION(dcb, 0x14972000, 16K, 4K) + REGION(pmic, 0x14976000, 40K, 4K) BSRAM_END(0x14980000) DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + RAMSTAGE(0x9F860000, 2M) } diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h index 299700a63f..c9883bc0bf 100644 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ b/src/soc/qualcomm/sdm845/include/soc/mmu.h @@ -16,8 +16,6 @@ #ifndef _SOC_QUALCOMM_SDM845_MMU_H__ #define _SOC_QUALCOMM_SDM845_MMU_H__ -#define DRAMSIZE4GB 0x100000000 - void sdm845_mmu_init(void); #endif // _SOC_QUALCOMM_SDM845_MMU_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index 1c14c03d01..e7bf1b2aea 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -17,10 +17,12 @@ #define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #include -#include DECLARE_REGION(ssram) DECLARE_REGION(bsram) DECLARE_REGION(dram_reserved) +DECLARE_REGION(dcb); +DECLARE_REGION(pmic); +DECLARE_REGION(limits_cfg); #endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ -- cgit v1.2.3