From 6bee0cee20fad2a3c68a9c54694807d9f2f48b0c Mon Sep 17 00:00:00 2001 From: Nitheesh Sekar Date: Fri, 14 Sep 2018 18:50:38 +0530 Subject: soc/qualcomm/qcs405: Add MMU support Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R Signed-off-by: Nitheesh Sekar Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/qualcomm/qcs405/mmu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/soc/qualcomm/qcs405/mmu.c (limited to 'src/soc/qualcomm/qcs405/mmu.c') diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c new file mode 100644 index 0000000000..a2d626fd35 --- /dev/null +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void qcs405_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), + MA_DEV | MA_S | MA_RW); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), MA_MEM | MA_S | MA_RW); + + mmu_enable(); +} -- cgit v1.2.3