From 20e75878a8ff47d18d87cd8d213d044cffcaeee7 Mon Sep 17 00:00:00 2001
From: Nitheesh Sekar <nsekar@codeaurora.org>
Date: Fri, 14 Sep 2018 11:24:10 +0530
Subject: soc/qualcomm/qcs405: Support for new SoC

Adding the basic infrastruture soc support for qcs405 and
a new build variant.

TEST=build

Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/soc/qualcomm/qcs405/Makefile.inc | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 src/soc/qualcomm/qcs405/Makefile.inc

(limited to 'src/soc/qualcomm/qcs405/Makefile.inc')

diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
new file mode 100644
index 0000000000..15f5a0c4d3
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -0,0 +1,32 @@
+
+ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y)
+
+################################################################################
+bootblock-y += bootblock.c
+bootblock-y += timer.c
+bootblock-y += spi.c
+
+################################################################################
+verstage-y += timer.c
+verstage-y += spi.c
+
+################################################################################
+romstage-y += timer.c
+romstage-y += spi.c
+romstage-y += cbmem.c
+
+################################################################################
+ramstage-y += soc.c
+ramstage-y += timer.c
+ramstage-y += spi.c
+ramstage-y += cbmem.c
+
+################################################################################
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	@printf "Generating: $(subst $(obj)/,,$(@))\n"
+	cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
+
+endif
-- 
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