From fa00ae7de6a9605deb5d1d8a930d2b0f4969e082 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Wed, 10 Dec 2014 20:11:30 -0800 Subject: google/storm: prepare enabling vboot2 This change sets up the list of source files for vboot2's verstage without enabling it. BRANCH=storm BUG=chrome-os-partner:34161 TEST=not much testing yet, just successful compilation. Change-Id: I4052c20795459bf0e057c0f0952226ea4a8c89f1 Signed-off-by: Patrick Georgi Original-Commit-Id: 48847ab8acfbe4b33d61d3d012c72c025cd8f364 Original-Change-Id: I1d7944e681f8a4b113a90ac028a0faba4423be89 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/234643 Reviewed-on: http://review.coreboot.org/9684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq806x/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/qualcomm/ipq806x') diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 16381a4de1..c0378bcdc9 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -23,6 +23,12 @@ bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c bootblock-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += clock.c +verstage-y += gpio.c +verstage-y += spi.c +verstage-y += timer.c +verstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart.c + romstage-y += clock.c romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c -- cgit v1.2.3