From d0037efda9e9ce855279d21b891d29edbfb664fb Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 18 Jan 2024 12:38:34 -0700 Subject: soc/*: Rename Makefiles from .inc to .mk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Felix Singer --- src/soc/qualcomm/ipq806x/Makefile.inc | 77 ----------------------------------- src/soc/qualcomm/ipq806x/Makefile.mk | 77 +++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 77 deletions(-) delete mode 100644 src/soc/qualcomm/ipq806x/Makefile.inc create mode 100644 src/soc/qualcomm/ipq806x/Makefile.mk (limited to 'src/soc/qualcomm/ipq806x') diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc deleted file mode 100644 index c01486d3a8..0000000000 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ /dev/null @@ -1,77 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOC_QC_IPQ806X),y) - -bootblock-y += clock.c -bootblock-y += gpio.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c -bootblock-y += timer.c -bootblock-y += uart.c - -verstage-y += clock.c -verstage-y += gpio.c -verstage-y += gsbi.c -verstage-y += i2c.c -verstage-y += qup.c -verstage-y += spi.c -verstage-y += timer.c -verstage-y += uart.c - -romstage-y += clock.c -romstage-y += blobs_init.c -romstage-y += gpio.c -romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-y += timer.c -romstage-y += uart.c -romstage-y += cbmem.c -romstage-y += i2c.c -romstage-y += gsbi.c -romstage-y += qup.c - -ramstage-y += blobs_init.c -ramstage-y += clock.c -ramstage-y += gpio.c -ramstage-y += lcc.c -ramstage-y += soc.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-y += timer.c -ramstage-y += uart.c # Want the UART always ready for the kernels' earlyprintk -ramstage-y += usb.c -ramstage-y += tz_wrapper.S -ramstage-y += gsbi.c -ramstage-y += i2c.c -ramstage-y += qup.c -ramstage-y += spi.c - -ifeq ($(CONFIG_USE_BLOBS),y) - -# Add MBN header to allow SBL3 to start coreboot bootblock -$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin - @printf " ADD MBN $(subst $(obj)/,,$(@))\n" - ./util/qualcomm/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp - @mv $@.tmp $@ - -# Create a complete bootblock which will start up the system -$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \ - $(objcbfs)/bootblock.mbn - @printf " MBNCAT $(subst $(obj)/,,$(@))\n" - @util/qualcomm/mbncat.py -o $@.tmp $^ - @mv $@.tmp $@ - -endif - -CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include - -# List of binary blobs coreboot needs in CBFS to be able to boot up this SOC -mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn - -# Location of the binary blobs -mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq806x - -# Create make variables to aid cbfs-files-handler in processing the blobs (add -# them all as raw binaries at the root level). -$(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\ - $(eval $(f)-file := $(mbn-root)/$(f))\ - $(eval $(f)-type := raw)) - -endif diff --git a/src/soc/qualcomm/ipq806x/Makefile.mk b/src/soc/qualcomm/ipq806x/Makefile.mk new file mode 100644 index 0000000000..c01486d3a8 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/Makefile.mk @@ -0,0 +1,77 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_QC_IPQ806X),y) + +bootblock-y += clock.c +bootblock-y += gpio.c +bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-y += timer.c +bootblock-y += uart.c + +verstage-y += clock.c +verstage-y += gpio.c +verstage-y += gsbi.c +verstage-y += i2c.c +verstage-y += qup.c +verstage-y += spi.c +verstage-y += timer.c +verstage-y += uart.c + +romstage-y += clock.c +romstage-y += blobs_init.c +romstage-y += gpio.c +romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-y += timer.c +romstage-y += uart.c +romstage-y += cbmem.c +romstage-y += i2c.c +romstage-y += gsbi.c +romstage-y += qup.c + +ramstage-y += blobs_init.c +ramstage-y += clock.c +ramstage-y += gpio.c +ramstage-y += lcc.c +ramstage-y += soc.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-y += timer.c +ramstage-y += uart.c # Want the UART always ready for the kernels' earlyprintk +ramstage-y += usb.c +ramstage-y += tz_wrapper.S +ramstage-y += gsbi.c +ramstage-y += i2c.c +ramstage-y += qup.c +ramstage-y += spi.c + +ifeq ($(CONFIG_USE_BLOBS),y) + +# Add MBN header to allow SBL3 to start coreboot bootblock +$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin + @printf " ADD MBN $(subst $(obj)/,,$(@))\n" + ./util/qualcomm/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp + @mv $@.tmp $@ + +# Create a complete bootblock which will start up the system +$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \ + $(objcbfs)/bootblock.mbn + @printf " MBNCAT $(subst $(obj)/,,$(@))\n" + @util/qualcomm/mbncat.py -o $@.tmp $^ + @mv $@.tmp $@ + +endif + +CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include + +# List of binary blobs coreboot needs in CBFS to be able to boot up this SOC +mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn + +# Location of the binary blobs +mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq806x + +# Create make variables to aid cbfs-files-handler in processing the blobs (add +# them all as raw binaries at the root level). +$(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\ + $(eval $(f)-file := $(mbn-root)/$(f))\ + $(eval $(f)-type := raw)) + +endif -- cgit v1.2.3