From 2f37bd65518865688b9234afce0d467508d6f465 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 19 Feb 2015 14:51:15 -0800 Subject: arm(64): Globally replace writel(v, a) with write32(a, v) This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq806x/qup.c | 80 +++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 40 deletions(-) (limited to 'src/soc/qualcomm/ipq806x/qup.c') diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index 25adfc18db..bc78e7c67a 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -51,9 +51,9 @@ static unsigned gsbi_qup_base[] = { static qup_return_t qup_i2c_master_status(gsbi_id_t gsbi_id) { - uint32_t reg_val = readl(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS)); + uint32_t reg_val = read32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS)); - if (readl(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS))) + if (read32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS))) return QUP_ERR_XFER_FAIL; if (reg_val & QUP_I2C_INVALID_READ_ADDR) return QUP_ERR_I2C_INVALID_SLAVE_ADDR; @@ -77,7 +77,7 @@ static int check_bit_state(uint32_t *reg, int wait_for) { unsigned int count = TIMEOUT_CNT; - while ((readl(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) != + while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) != (QUP_STATE_VALID | wait_for)) { if (count == 0) return QUP_ERR_TIMEOUT; @@ -103,14 +103,14 @@ qup_return_t qup_reset_i2c_master_status(gsbi_id_t gsbi_id) * Bit31-25, Bit1 and Bit0 are reserved. */ //TODO: Define each status bit. OR all status bits in a single macro. - writel(0x3FFFFFC, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS)); + write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_STATUS), 0x3FFFFFC); return QUP_SUCCESS; } static qup_return_t qup_reset_master_status(gsbi_id_t gsbi_id) { - writel(0x7C, QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS)); - writel(0x7C, QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS_EN)); + write32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS), 0x7C); + write32(QUP_ADDR(gsbi_id, QUP_ERROR_FLAGS_EN), 0x7C); qup_reset_i2c_master_status(gsbi_id); return QUP_SUCCESS; } @@ -120,7 +120,7 @@ static qup_return_t qup_fifo_wait_for(gsbi_id_t gsbi_id, uint32_t status) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned int count = TIMEOUT_CNT; - while (!(readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status)) { + while (!(read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status)) { ret = qup_i2c_master_status(gsbi_id); if (ret) return ret; @@ -137,7 +137,7 @@ static qup_return_t qup_fifo_wait_while(gsbi_id_t gsbi_id, uint32_t status) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned int count = TIMEOUT_CNT; - while (readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status) { + while (read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & status) { ret = qup_i2c_master_status(gsbi_id); if (ret) return ret; @@ -161,16 +161,16 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, qup_reset_master_status(gsbi_id); qup_set_state(gsbi_id, QUP_STATE_RUN); - writel((QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr)), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr))); while (data_len) { if (data_len == 1 && stop_seq) { - writel((QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx])), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data_ptr[idx]))); } else { - writel((QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx])), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data_ptr[idx]))); } data_len--; idx++; @@ -187,10 +187,10 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, means that software knows to return to fill the output FIFO with data. */ - if (readl(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & + if (read32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL)) & OUTPUT_SERVICE_FLAG) { - writel(OUTPUT_SERVICE_FLAG, - QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), + OUTPUT_SERVICE_FLAG); } } @@ -234,17 +234,17 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) qup_reset_master_status(gsbi_id); qup_set_state(gsbi_id, QUP_STATE_RUN); - writel((QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_START_SEQ | (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ))); - writel((QUP_I2C_RECV_SEQ | data_len), - QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO)); + write32(QUP_ADDR(gsbi_id, QUP_OUTPUT_FIFO), + (QUP_I2C_RECV_SEQ | data_len)); ret = qup_fifo_wait_while(gsbi_id, OUTPUT_FIFO_NOT_EMPTY); if (ret) return ret; - writel(OUTPUT_SERVICE_FLAG, QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG); while (data_len) { uint32_t data; @@ -253,7 +253,7 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) if (ret) return ret; - data = readl(QUP_ADDR(gsbi_id, QUP_INPUT_FIFO)); + data = read32(QUP_ADDR(gsbi_id, QUP_INPUT_FIFO)); /* * Process tag and corresponding data value. For I2C master @@ -268,8 +268,8 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) data_ptr[idx] = QUP_I2C_DATA(data); idx++; data_len--; - writel(INPUT_SERVICE_FLAG, - QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), + INPUT_SERVICE_FLAG); } else if (QUP_I2C_MI_TAG(data) == QUP_I2C_MISTOP_SEQ) { /* Tag: MISTOP: Last byte of master input. */ data_ptr[idx] = QUP_I2C_DATA(data); @@ -282,7 +282,7 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) } } - writel(INPUT_SERVICE_FLAG, QUP_ADDR(gsbi_id, QUP_OPERATIONAL)); + write32(QUP_ADDR(gsbi_id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG); p_tx_obj->p.iic.data_len = idx; qup_set_state(gsbi_id, QUP_STATE_PAUSE); @@ -316,7 +316,7 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) uint32_t reg_val; /* Reset the QUP core.*/ - writel(0x1, QUP_ADDR(gsbi_id, QUP_SW_RESET)); + write32(QUP_ADDR(gsbi_id, QUP_SW_RESET), 0x1); /*Wait till the reset takes effect */ ret = qup_wait_for_state(gsbi_id, QUP_STATE_RESET); @@ -324,7 +324,7 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) goto bailout; /* Reset the config */ - writel(0, QUP_ADDR(gsbi_id, QUP_CONFIG)); + write32(QUP_ADDR(gsbi_id, QUP_CONFIG), 0); /*Program the config register*/ /*Set N value*/ @@ -340,10 +340,10 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) ret = QUP_ERR_UNSUPPORTED; goto bailout; } - writel(reg_val, QUP_ADDR(gsbi_id, QUP_CONFIG)); + write32(QUP_ADDR(gsbi_id, QUP_CONFIG), reg_val); /*Reset i2c clk cntl register*/ - writel(0, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL)); + write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL), 0); /*Set QUP IO Mode*/ switch (config_ptr->mode) { @@ -358,14 +358,14 @@ qup_return_t qup_init(gsbi_id_t gsbi_id, const qup_config_t *config_ptr) ret = QUP_ERR_UNSUPPORTED; goto bailout; } - writel(reg_val, QUP_ADDR(gsbi_id, QUP_IO_MODES)); + write32(QUP_ADDR(gsbi_id, QUP_IO_MODES), reg_val); /*Set i2c clk cntl*/ reg_val = (QUP_DIVIDER_MIN_VAL << QUP_HS_DIVIDER_SHFT); reg_val |= ((((config_ptr->src_frequency / config_ptr->clk_frequency) / 2) - QUP_DIVIDER_MIN_VAL) & QUP_FS_DIVIDER_MASK); - writel(reg_val, QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL)); + write32(QUP_ADDR(gsbi_id, QUP_I2C_MASTER_CLK_CTL), reg_val); bailout: if (ret) @@ -377,7 +377,7 @@ bailout: qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state) { qup_return_t ret = QUP_ERR_UNDEFINED; - unsigned curr_state = readl(QUP_ADDR(gsbi_id, QUP_STATE)); + unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE)); if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE) && (curr_state & QUP_STATE_VALID_MASK)) { @@ -387,10 +387,10 @@ qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state) * transition to complete. */ if (QUP_STATE_PAUSE == curr_state && QUP_STATE_RESET == state) { - writel(0x2, QUP_ADDR(gsbi_id, QUP_STATE)); - writel(0x2, QUP_ADDR(gsbi_id, QUP_STATE)); + write32(QUP_ADDR(gsbi_id, QUP_STATE), 0x2); + write32(QUP_ADDR(gsbi_id, QUP_STATE), 0x2); } else { - writel(state, QUP_ADDR(gsbi_id, QUP_STATE)); + write32(QUP_ADDR(gsbi_id, QUP_STATE), state); } ret = qup_wait_for_state(gsbi_id, state); } @@ -402,7 +402,7 @@ static qup_return_t qup_i2c_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, uint8_t stop_seq) { qup_return_t ret = QUP_ERR_UNDEFINED; - uint8_t mode = (readl(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> + uint8_t mode = (read32(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK; ret = qup_i2c_write(gsbi_id, mode, p_tx_obj, stop_seq); @@ -423,7 +423,7 @@ qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, { qup_return_t ret = QUP_ERR_UNDEFINED; - if (p_tx_obj->protocol == ((readl(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> + if (p_tx_obj->protocol == ((read32(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { switch (p_tx_obj->protocol) { case QUP_MINICORE_I2C_MASTER: @@ -440,7 +440,7 @@ qup_return_t qup_send_data(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, static qup_return_t qup_i2c_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_rx_obj) { qup_return_t ret = QUP_ERR_UNDEFINED; - uint8_t mode = (readl(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> + uint8_t mode = (read32(QUP_ADDR(gsbi_id, QUP_IO_MODES)) >> QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK; ret = qup_i2c_read(gsbi_id, mode, p_rx_obj); @@ -460,7 +460,7 @@ qup_return_t qup_recv_data(gsbi_id_t gsbi_id, qup_data_t *p_rx_obj) { qup_return_t ret = QUP_ERR_UNDEFINED; - if (p_rx_obj->protocol == ((readl(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> + if (p_rx_obj->protocol == ((read32(QUP_ADDR(gsbi_id, QUP_CONFIG)) >> QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { switch (p_rx_obj->protocol) { case QUP_MINICORE_I2C_MASTER: -- cgit v1.2.3