From 46514c2b877c29c2d7c2061a9785736e270c0c62 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 11 Jun 2020 11:59:07 -0700 Subject: treewide: Add Kconfig variable MEMLAYOUT_LD_FILE This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/ipq806x/memlayout.ld | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 src/soc/qualcomm/ipq806x/memlayout.ld (limited to 'src/soc/qualcomm/ipq806x/memlayout.ld') diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld new file mode 100644 index 0000000000..6e7e56cada --- /dev/null +++ b/src/soc/qualcomm/ipq806x/memlayout.ld @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +SECTIONS +{ + REGION(rpm, 0x00020000, 160K, 8K) + SRAM_START(0x2A000000) + /* This includes bootblock image, can be reused after bootblock starts */ +/* UBER_SBL(0x2A000000, 48K) */ +/* DDR(0x2A000000, 48K) */ + BOOTBLOCK(0x2A00C000, 24K) + OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K) + VBOOT2_WORK(0x2A022000, 12K) + PRERAM_CBMEM_CONSOLE(0x2A026000, 32K) + TIMESTAMP(0x2A02E000, 1K) + +/* 0x2e400..0x3F000 67 KB free */ + +/* Keep the below area reserved at all times, it is used by various QCA + components as shared data + QCA_SHARED_RAM(2A03F000, 4K) +*/ + STACK(0x2A040000, 16K) + PRERAM_CBFS_CACHE(0x2A044000, 91K) + FMAP_CACHE(0x2A05B000, 2K) + TTB_SUBTABLES(0x2A05B800, 2K) + TTB(0x2A05C000, 16K) + SRAM_END(0x2A060000) + + DRAM_START(0x40000000) + RAMSTAGE(0x40640000, 128K) + SYMBOL(memlayout_cbmem_top, 0x59F80000) + POSTRAM_CBFS_CACHE(0x59F80000, 384K) + DMA_COHERENT(0x5A000000, 2M) +} -- cgit v1.2.3