From 18e434d1d35f96d5cf6a4b6c14f5528019c4f2f4 Mon Sep 17 00:00:00 2001 From: Deepa Dinamani Date: Wed, 10 Dec 2014 15:23:47 -0800 Subject: storm: Add watchdog reset api. Use the apps processor watchdog reset to do a hard reset. The watchdog reset drives the RESETOUT on the chip. Modify register address definitions to be able to use pointers and pointer arithmetics. BRANCH=storm BUG=chrome-os-partner:34334 TEST=the chip resets and the control returns to start of SBL. Change-Id: Ib5772ab152b27058fde1be9de2d2ac26bfe00ca4 Signed-off-by: Patrick Georgi Original-Commit-Id: d50413cb614ef05ada93be1252fe5ef617a94d91 Original-Change-Id: I9b249d057b473429335587f7241ca462b4a6a8b7 Original-Signed-off-by: Deepa Dinamani Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/236141 Original-Reviewed-by: Trevor Bourget Reviewed-on: http://review.coreboot.org/9691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq806x/include/soc/iomap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/qualcomm/ipq806x/include') diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index 333e2615eb..129b17700c 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -49,9 +49,9 @@ #define clrsetbits_le32_i(addr, clear, set) \ clrsetbits_le32(((void *)(addr)), (clear), (set)) -#define MSM_CLK_CTL_BASE 0x00900000 +#define MSM_CLK_CTL_BASE ((unsigned char *)0x00900000) -#define MSM_TMR_BASE 0x0200A000 +#define MSM_TMR_BASE ((unsigned char *)0x0200A000) #define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) -- cgit v1.2.3