From ef77f873721afc52d988c0291e26ed90dbc8ea55 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Wed, 10 Dec 2014 20:42:58 -0800 Subject: ipq8064: add DRAM initialization code Read two blobs from CBFS: cdt.mbn (memory configuration descriptor) and ddr.mbn (actual memory initialization code). Pointer to CDT which starts right above the MBN header is passed to the memory initialization routine. Zero return value means memory initialization succeeded. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with upcoming patches memory initialization succeeds. Change-Id: Ia0903dc4446c03f7f0dc3f4cc3a34e90a8064afc Signed-off-by: Patrick Georgi Original-Commit-Id: 1d79dadd7d47dd6d01e031bc77810c9e85dd854b Original-Change-Id: Ib5a7e4fe0eb24a7bd090ec3553c57cd1b7e41512 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/234644 Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/9686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq806x/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/qualcomm/ipq806x/Makefile.inc') diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 0d5d59ca7f..7fb6290a42 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -33,6 +33,7 @@ verstage-y += timer.c verstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart.c romstage-y += clock.c +romstage-y += blobs_init.c romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c -- cgit v1.2.3