From 3cfb6a066b6801186b716a4f789b69655e1e420e Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Wed, 11 Feb 2015 15:13:04 -0800 Subject: ipq806x: add LPASS clock control driver Add a clock control driver to initialize the clock tree inside the low-power audio subsystem. Depthcharge builds up on this to enable audio function on storm. The clock is hardcoded for 48KHz frame rate, two 16 bit channels. BRANCH=storm BUG=chrome-os-partner:35247 TEST=with depthcharge patches applied and Using depthcharge CLI audio test program verified that the target generates sensible sounds audio 100 100 audio 1000 5000 Change-Id: I56513fc782657ade99b6e43b2d5d3141d27ecc4e Signed-off-by: Patrick Georgi Original-Commit-Id: 0d4f408408aa38b2f0ee19b83ed490de39074760 Original-Change-Id: If8ffc326698fcea17e05d536930d927ca553481f Original-Signed-off-by: Kenneth Westfield Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/248830 Original-Reviewed-by: Dylan Reid Reviewed-on: http://review.coreboot.org/9758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq806x/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/qualcomm/ipq806x/Makefile.inc') diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index e0f014af35..80bd0587b1 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += blobs_init.c ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c +ramstage-y += lcc.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += timer.c -- cgit v1.2.3