From 08f249e7d07e7742e202d08305822af2b3ddec78 Mon Sep 17 00:00:00 2001 From: Vikas Das Date: Mon, 22 Sep 2014 17:49:56 -0700 Subject: ipq806x: Load TZBSP blob from coreboot ramstage Read the TZBSP blob from CBFS and run it. A side effect of the blob execution is switching the processor into User mode. Starting TZBSP requires processor running in Supervisor mode, TZBSP code is compiled for ARM. Coreboot is executing in System mode and is compiled for Thumb. An assembler wrapper switches the execution mode and interfaces between Thumb and ARM modes. BUG=chrome-os-partner:34161 BRANCH=Storm TEST=manual With the preceeding patches the system successfully loads to depthcharge in recovery mode. Change-Id: I812b5cef95ba5562a005e005162d6391e502ecf8 Signed-off-by: Patrick Georgi Original-Commit-Id: 7065cf3d17964a1d9038ec8906b469a08a79c6e2 Original-Change-Id: Ib14dbcbcbe489b595f4247d489d50f76a0e65948 Original-Signed-off-by: Varadarajan Narayanan Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/229026 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq806x/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/qualcomm/ipq806x/Makefile.inc') diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 7fb6290a42..e0f014af35 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -40,6 +40,7 @@ romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c +ramstage-y += blobs_init.c ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c @@ -48,6 +49,7 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += usb.c +ramstage-y += tz_wrapper.S ifeq ($(CONFIG_USE_BLOBS),y) -- cgit v1.2.3