From 6fbc763b816633653810e8b1a745b375fa9606c8 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Wed, 6 Jan 2016 14:13:25 +0530 Subject: soc/qualcomm/ipq40xx: Enable crashdump handling Clear the crash dump cookie set by SBL to indicate that it is a normal reset. Inform DDR image of the entrypoint for SDI image to be preserved in OCIMEM which will be needed during watchdog resets. BUG=chrome-os-partner:49249 TEST=DDR image is able to fetch the entry point address BRANCH=none Change-Id: I3e6e4a108585bb257e3ad02956c420acbcb2554e Signed-off-by: Patrick Georgi Original-Commit-Id: bd726256a5ae89672810b57e1d2a7a9287f60627 Original-Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660 Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333321 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Reviewed-by: David Hendricks Reviewed-on: https://review.coreboot.org/14679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq40xx/include/soc/iomap.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/qualcomm/ipq40xx/include') diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h index bfdfb56f8e..0bc8a30a70 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h @@ -130,6 +130,9 @@ enum { #define BLSP1_QUP2_BASE ((void *)0x078B7000) #define BLSP1_QUP3_BASE ((void *)0x078B8000) +#define TCSR_BOOT_MISC_DETECT ((void *)0x0193D100) +#define TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000) + static inline void *blsp_qup_base(blsp_qup_id_t id) { switch (id) { -- cgit v1.2.3