From 2596764f34a03e4f53704ca5efef71de5c4f9f4c Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 8 Mar 2016 15:02:56 +0530 Subject: soc/qualcomm/ipq40xx: Add support for BLSP QUP I2C Able to talk to the TPM device and the commands seem to succeed. BUG=chrome-os-partner:49249 chrome-os-partner:49250 TEST=All commands to the TPM succeed BRANCH=none Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019 Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333314 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Reviewed-by: David Hendricks squashed: soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI - Enable BLSP SPI driver for ipq40xx - supports only FIFO mode BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9 Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870 Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333303 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Reviewed-by: David Hendricks Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/14677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/qualcomm/ipq40xx/clock.c | 67 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) (limited to 'src/soc/qualcomm/ipq40xx/clock.c') diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c index fab0c9e07a..864f2b603b 100644 --- a/src/soc/qualcomm/ipq40xx/clock.c +++ b/src/soc/qualcomm/ipq40xx/clock.c @@ -28,8 +28,10 @@ */ #include +#include #include #include +#include #define CLOCK_UPDATE_DELAY 1000 @@ -67,6 +69,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, udelay(1); } + /* Please refer to the comments in blsp_i2c_clock_config() */ setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); } @@ -110,3 +113,67 @@ void usb_clock_config(void) udelay(5); write32(USB30_RESET, 0); /* deassert all USB resets again */ } + +int blsp_i2c_clock_config(blsp_qup_id_t id) +{ + int i; + const int max_tries = 200; + struct { void *cbcr, *cmd, *cfg; } clk[] = { + { + GCC_BLSP1_QUP1_I2C_APPS_CBCR, + GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR, + GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR, + }, + { + GCC_BLSP1_QUP1_I2C_APPS_CBCR, + GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR, + GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR, + }, + { + GCC_BLSP1_QUP1_I2C_APPS_CBCR, + GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR, + GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR, + }, + { + GCC_BLSP1_QUP1_I2C_APPS_CBCR, + GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR, + GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR, + }, + }; + + /* + * uart_clock_config() does this. Ideally, setting these bits once + * should suffice. However, if for some reason the order of invocation + * of uart_clock_config and blsp_i2c_clock_config gets changed or + * something, then one of the functions might not work. Hence, to steer + * clear of such dependencies, just replicating the setting of this + * bits. + * + * Moreover, they are read-modify-write and HW wise repeated setting of + * the same bits is harmless. Hence repeating them here should be ok. + * This will ensure root and branch clocks remain on. + */ + setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); + + /* Src Sel 1 (fepll 200), Src Div 10.5 */ + write32(clk[id].cfg, (1u << 8) | (20u << 0)); + + write32(clk[id].cmd, BIT(0)); /* Update En */ + + for (i = 0; i < max_tries; i++) { + if (read32(clk[id].cmd) & BIT(0)) { + udelay(5); + continue; + } + break; + } + + if (i == max_tries) { + printk(BIOS_ERR, "%s failed\n", __func__); + return -ETIMEDOUT; + } + + write32(clk[id].cbcr, BIT(0)); /* Enable */ + + return 0; +} -- cgit v1.2.3