From afaa3d0356d5a518442701875505901e5806bb61 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Tue, 6 Oct 2020 15:50:21 -0700 Subject: trogdor: Modify DDR training to use mrc_cache Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table. BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots. Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/common/include/soc/qclib_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/qualcomm/common/include') diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index e8dc499fb6..c906ef2f73 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -11,7 +11,6 @@ #define QCLIB_TE_NAME_LENGTH 24 /* FMAP_REGION names */ -#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING" #define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG" /* TE_NAME (table entry name) */ -- cgit v1.2.3