From ca7794854c9d04d1fcd95c2e1170265b8a36297b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 1 Jul 2015 13:55:10 -0700 Subject: tegra132: adjust vboot2 memlayout to make coreboot compile romstage didn't fit in it's region anymore. Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/10759 Reviewed-by: Marc Jones Tested-by: build bot (Jenkins) --- src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/nvidia') diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index a834f99914..2fba8ef7e8 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -36,9 +36,9 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) - BOOTBLOCK(0x40019000, 24K) - VERSTAGE(0x4001f000, 60K) - ROMSTAGE(0x4002e000, 72K) + BOOTBLOCK(0x40019000, 22K) + VERSTAGE(0x4001e800, 58K) + ROMSTAGE(0x4002d000, 76K) SRAM_END(0x40040000) DRAM_START(0x80000000) -- cgit v1.2.3