From 809aeeed98104c016a5ee1cdd5009a84a5611d8e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Aug 2018 12:14:33 +0200 Subject: src/soc: Fix typo Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/nvidia/tegra124/chip.h | 2 +- src/soc/nvidia/tegra124/sdram_lp0.c | 2 +- src/soc/nvidia/tegra210/chip.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/nvidia') diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 6994ca2210..d9ab67bf5f 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -88,7 +88,7 @@ struct soc_nvidia_tegra124_config { int pixel_clock; - /* The minimum link configuraton settings */ + /* The minimum link configuration settings */ u32 lane_count; u32 enhanced_framing; u32 link_bw; diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index d5019d9ef8..536ad31804 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -23,7 +23,7 @@ #include /* - * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from + * This function reads SDRAM parameters (and a few CLK_RST register values) from * the common BCT format and writes them into PMC scratch registers (where the * BootROM expects them on LP0 resume). Since those store the same values in a * different format, we follow a "translation table" taken from Nvidia's U-Boot diff --git a/src/soc/nvidia/tegra210/chip.h b/src/soc/nvidia/tegra210/chip.h index 6a2aa84ab0..75d2497186 100644 --- a/src/soc/nvidia/tegra210/chip.h +++ b/src/soc/nvidia/tegra210/chip.h @@ -76,7 +76,7 @@ struct soc_nvidia_tegra210_config { int hpd_plug_min_us; int hpd_irq_min_us; - /* The minimum link configuraton settings */ + /* The minimum link configuration settings */ u32 lane_count; u32 enhanced_framing; u32 link_bw; -- cgit v1.2.3