From 42f15054b178efe9a4d1c8a4e0c203d1aa4aad01 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 7 Oct 2023 11:16:43 +0200 Subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin Reviewed-by: Kyösti Mälkki Reviewed-by: Julius Werner --- src/soc/nvidia/tegra124/memlayout.ld | 2 +- src/soc/nvidia/tegra210/memlayout.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/nvidia') diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld index ed386f1fdc..6f507ae2ba 100644 --- a/src/soc/nvidia/tegra124/memlayout.ld +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -29,6 +29,6 @@ SECTIONS DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 128K) + RAMSTAGE(0x80200000, 2M) DMA_COHERENT(0x90000000, 2M) } diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld index 55da1293d9..e272c7d449 100644 --- a/src/soc/nvidia/tegra210/memlayout.ld +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -32,6 +32,6 @@ SECTIONS DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 256K) + RAMSTAGE(0x80200000, 2M) TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) } -- cgit v1.2.3