From 038e7247dc9705ff2d47dd90ec9a807f6feb52ba Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 29 Jul 2016 18:31:16 +0200 Subject: src/soc: Capitalize CPU, ACPI, RAM and ROM Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth --- src/soc/nvidia/tegra124/bootblock.c | 2 +- src/soc/nvidia/tegra124/bootblock_asm.S | 2 +- src/soc/nvidia/tegra124/include/soc/sdram_param.h | 4 ++-- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 2 +- src/soc/nvidia/tegra124/maincpu.S | 2 +- src/soc/nvidia/tegra132/bootblock_asm.S | 2 +- src/soc/nvidia/tegra132/ccplex.c | 4 ++-- src/soc/nvidia/tegra132/clock.c | 2 +- src/soc/nvidia/tegra132/include/soc/sdram_param.h | 4 ++-- src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c | 2 +- src/soc/nvidia/tegra132/romstage.c | 2 +- src/soc/nvidia/tegra210/bootblock_asm.S | 2 +- src/soc/nvidia/tegra210/ccplex.c | 2 +- src/soc/nvidia/tegra210/include/soc/sdram_param.h | 4 ++-- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 2 +- src/soc/nvidia/tegra210/romstage.c | 2 +- 16 files changed, 20 insertions(+), 20 deletions(-) (limited to 'src/soc/nvidia') diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 2a526a7748..ce41242299 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -34,7 +34,7 @@ static void run_next_stage(void *entry) power_enable_and_ungate_cpu(); - /* Repair ram on cluster0 and cluster1 after CPU is powered on. */ + /* Repair RAM on cluster0 and cluster1 after CPU is powered on. */ ram_repair(); clock_cpu0_remove_reset(); diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index 5484450f02..0391ebf1ac 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -28,7 +28,7 @@ ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 2d0ba7d7c1..a67a009945 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -791,9 +791,9 @@ struct sdram_params { uint32_t EmcCaTrainingTimingCntl2; /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ uint32_t McMtsCarveoutBom; diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 8a0d038712..2737b282e0 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -612,7 +612,7 @@ void lp0_resume(void) power_on_main_cpu(); - // Perform ram repair after cpu is powered on. + // Perform RAM repair after CPU is powered on. ram_repair(); clear_cpu_resets(); diff --git a/src/soc/nvidia/tegra124/maincpu.S b/src/soc/nvidia/tegra124/maincpu.S index 11367480ad..fc32ed2637 100644 --- a/src/soc/nvidia/tegra124/maincpu.S +++ b/src/soc/nvidia/tegra124/maincpu.S @@ -32,7 +32,7 @@ .arm ENTRY(maincpu_setup) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra132/bootblock_asm.S b/src/soc/nvidia/tegra132/bootblock_asm.S index 857900a6eb..62554422db 100644 --- a/src/soc/nvidia/tegra132/bootblock_asm.S +++ b/src/soc/nvidia/tegra132/bootblock_asm.S @@ -30,7 +30,7 @@ ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index 5a307b57bb..95f91d8f8d 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -133,14 +133,14 @@ static void request_ram_repair(void) stopwatch_init(&sw); - /* Perform cluster 0 ram repair */ + /* Perform cluster 0 RAM repair */ reg = read32(&flow->ram_repair); reg |= req; write32(&flow->ram_repair, reg); while ((read32(&flow->ram_repair) & sts) != sts) ; - /* Perform cluster 1 ram repair */ + /* Perform cluster 1 RAM repair */ reg = read32(&flow->ram_repair_cluster1); reg |= req; write32(&flow->ram_repair_cluster1, reg); diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 0db120d8d2..be12b856b1 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -508,7 +508,7 @@ void clock_cpu0_config(void) /* wait and try again */ if (timeout >= CLK_SWITCH_TIMEOUT_US) { printk(BIOS_ERR, "%s: PLLX programming timeout. " - "Switching cpu clock has falied.\n", + "Switching CPU clock has falied.\n", __func__); break; } diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_param.h b/src/soc/nvidia/tegra132/include/soc/sdram_param.h index 6bc5aeaf49..ce85058383 100644 --- a/src/soc/nvidia/tegra132/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra132/include/soc/sdram_param.h @@ -794,9 +794,9 @@ struct sdram_params { /* Set if bit 6 select is greater than bit 7 select; uses aremc. spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ uint32_t McMtsCarveoutBom; diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c index 94d22634a4..bd4e5c4218 100644 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c @@ -645,7 +645,7 @@ void lp0_resume(void) power_on_main_cpu(); - // Perform ram repair after cpu is powered on. + // Perform RAM repair after CPU is powered on. ram_repair(); clear_cpu_resets(); diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 3b45aff63d..c5c1392c07 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -72,7 +72,7 @@ void romstage(void) cbmem_initialize_empty(); ccplex_cpu_prepare(); - printk(BIOS_INFO, "T132 romstage: cpu prepare done\n"); + printk(BIOS_INFO, "T132 romstage: CPU prepare done\n"); ccplex_load_mts(); printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); diff --git a/src/soc/nvidia/tegra210/bootblock_asm.S b/src/soc/nvidia/tegra210/bootblock_asm.S index 857900a6eb..62554422db 100644 --- a/src/soc/nvidia/tegra210/bootblock_asm.S +++ b/src/soc/nvidia/tegra210/bootblock_asm.S @@ -30,7 +30,7 @@ ENTRY(_start) /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are * installed, but at least the problem will show up near the code that * causes it. diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index a652b7624e..8759c73227 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -72,7 +72,7 @@ static void request_ram_repair(void) stopwatch_init(&sw); - /* Perform ram repair */ + /* Perform RAM repair */ reg = read32(&flow->ram_repair); reg |= req; write32(&flow->ram_repair, reg); diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 667d090118..dee7c7caab 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -951,9 +951,9 @@ struct sdram_params { /* Set if bit 6 select is greater than bit 7 select; uses aremc. spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 15477d6fe2..d3ac67b00f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -1024,7 +1024,7 @@ void lp0_resume(void) * 1 : MAX77621 */ if (read32(pmc_scratch201_ptr) & PMIC_77621) - /* Set cpu rail 0.85V */ + /* Set CPU rail 0.85V */ i2c_send(MAX77621_I2C_ADDR, MAX77621_VOUT_DATA); else /* Enable GPIO5 on MAX77620 PMIC */ diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index c9ff35bfb5..9491570a0b 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -79,7 +79,7 @@ void romstage(void) cbmem_initialize_empty(); ccplex_cpu_prepare(); - printk(BIOS_INFO, "T210 romstage: cpu prepare done\n"); + printk(BIOS_INFO, "T210 romstage: CPU prepare done\n"); romstage_mainboard_init(); -- cgit v1.2.3