From fff922bd14bca42841df88e940680766cdcfb431 Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Tue, 6 Jan 2015 15:08:54 -0800 Subject: rush: Enable dp display Add dp/sor supporting functions to enable dp panel. BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush and ryu Change-Id: I1cc5a95ef5e3ea7cc701c1cb124a7eb5a5dbd872 Signed-off-by: Patrick Georgi Original-Commit-Id: 795a7cddd36bd783cfdd6f1d3f7092bf48ebd8e7 Original-Change-Id: I336336dbbc5a772eec19ba96db8e7b50f6ea1497 Original-Signed-off-by: Jimmy Zhang Original-Reviewed-on: https://chromium-review.googlesource.com/238945 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9616 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra/dc.h | 19 +++++++++++++++++++ src/soc/nvidia/tegra/displayport.h | 2 ++ 2 files changed, 21 insertions(+) (limited to 'src/soc/nvidia/tegra') diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 88080082b2..0908b15c6d 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -501,6 +501,25 @@ struct tegra_dc { void *base; }; +struct tegra_dc_mode { + int pclk; + int rated_pclk; + int h_ref_to_sync; + int v_ref_to_sync; + int h_sync_width; + int v_sync_width; + int h_back_porch; + int v_back_porch; + int h_active; + int v_active; + int h_front_porch; + int v_front_porch; + int stereo_mode; + u32 flags; + u8 avi_m; + u32 vmode; +}; + unsigned long READL(void * p); void WRITEL(unsigned long value, void * p); diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h index b7face5d4e..9de056077c 100644 --- a/src/soc/nvidia/tegra/displayport.h +++ b/src/soc/nvidia/tegra/displayport.h @@ -439,6 +439,8 @@ struct tegra_dc_dp_data { #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000) #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001) +#define NV_DPCD_SINK_STATUS (0x00000205) +#define NV_DPCD_SINK_STATUS_PORT0_IN_SYNC (0x1 << 0) #define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206) #define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207) #define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0 -- cgit v1.2.3