From edf6b57f73e3cafaecd67a71fdf7313e75c1b3e8 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 25 Oct 2013 17:49:26 -0700 Subject: tegra124/nyan: display, clock, and other updates tegra124: Set Tx FIFO threshold value to recommended setting Reviewed-on: https://chromium-review.googlesource.com/175200 (cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad) tegra124: add CLK_X definitions Reviewed-on: https://chromium-review.googlesource.com/175220 (cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d) tegra124: fix incorrect struct member in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/175270 (cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c) tegra124: add the _x clocks to clock_enable_clear_reset Reviewed-on: https://chromium-review.googlesource.com/175539 (cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5) tegra124: add clock support code for graphics. Reviewed-on: https://chromium-review.googlesource.com/175162 (cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819) tegra124: Clean up some #defines for DMA Reviewed-on: https://chromium-review.googlesource.com/175631 (cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9) tegra124: enable flow control for APBDMA in SPI driver Reviewed-on: https://chromium-review.googlesource.com/175630 (cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d) nyan: move clock setup for the display out of dca_init Reviewed-on: https://chromium-review.googlesource.com/175656 (cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc) tegra124: more display PLL setup and clock hardcode removal. Reviewed-on: https://chromium-review.googlesource.com/175732 (cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f) tegra124: move dp.c from tegra to tegra124 Reviewed-on: https://chromium-review.googlesource.com/175830 (cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0) tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb Reviewed-on: https://chromium-review.googlesource.com/175889 (cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484) tegra: get rid of struct members that are not used Reviewed-on: https://chromium-review.googlesource.com/176023 (cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6) tegra124: Increase SCLK (AVP) to 300MHz Reviewed-on: https://chromium-review.googlesource.com/175489 (cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552) tegra124: Address old main CPU starting review feedback. Reviewed-on: https://chromium-review.googlesource.com/175933 (cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd) tegra124: Revise clock source configuration for irregular peripherals. Reviewed-on: https://chromium-review.googlesource.com/176109 (cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99) nyan: add timestamps in romstage Reviewed-on: https://chromium-review.googlesource.com/176172 (cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935) tegra124: Allow enabling clock output for external peripherals. Reviewed-on: https://chromium-review.googlesource.com/176108 (cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed) nyan: Enable and configure clocks for I2S and audio codec. Reviewed-on: https://chromium-review.googlesource.com/176104 (cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4) tegra124: Fix typo in pinmux name. Reviewed-on: https://chromium-review.googlesource.com/176215 (cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34) nyan: Add pinmux settings for audio peripherals. Reviewed-on: https://chromium-review.googlesource.com/176212 (cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c) nyan: De-array-ify the PMIC setup code. Reviewed-on: https://chromium-review.googlesource.com/176903 (cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247) nyan: Add a kconfig for building for the original nyans in pixel cases. Reviewed-on: https://chromium-review.googlesource.com/176904 (cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed) nyan: Set the CPU voltage differently depending on which PMIC is in use. Reviewed-on: https://chromium-review.googlesource.com/176905 (cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc) nyan: Increase the CPU voltage to 1.2V. Reviewed-on: https://chromium-review.googlesource.com/176906 (cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557) tegra124: Flesh out/tidy up the flow controller constants. Reviewed-on: https://chromium-review.googlesource.com/177085 (cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794) tegra124: When leaving the bootblock/AVP, really stop the AVP. Reviewed-on: https://chromium-review.googlesource.com/177086 (cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd) nyan: Set SPI4 speed to 33MHz Reviewed-on: https://chromium-review.googlesource.com/177038 (cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55) nyan: Do console_init() in romstage Reviewed-on: https://chromium-review.googlesource.com/176763 (cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03) nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option. Reviewed-on: https://chromium-review.googlesource.com/177486 (cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba) nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin. Reviewed-on: https://chromium-review.googlesource.com/177487 (cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f) tegra124: Bump up HCLK and PCLK Reviewed-on: https://chromium-review.googlesource.com/177563 (cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405) nyan: Add some code for reading the board ID. Reviewed-on: https://chromium-review.googlesource.com/177488 (cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f) nyan: Use the board ID to decide how to initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/177489 (cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c) nyan: Create kconfig variables for each SDRAM config. Reviewed-on: https://chromium-review.googlesource.com/177580 (cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377) tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line. Reviewed-on: https://chromium-review.googlesource.com/177637 (cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9) tegra124: Initialize the MCR when setting up the UART. Reviewed-on: https://chromium-review.googlesource.com/177638 (cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6) tegra124: fix SPI AHB burst length Reviewed-on: https://chromium-review.googlesource.com/177564 (cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315) tegra124: remove unneeded debug print in SPI code Reviewed-on: https://chromium-review.googlesource.com/177833 (cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06) nyan: Set up the SOC and TPM reset pin. Reviewed-on: https://chromium-review.googlesource.com/177965 (cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a) tegra124: Allow some time for packets to appear in Rx FIFO Reviewed-on: https://chromium-review.googlesource.com/177832 (cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84) nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722 Reviewed-on: https://chromium-review.googlesource.com/178226 (cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a) nyan: change devicetree for the new display settings. Reviewed-on: https://chromium-review.googlesource.com/177958 (cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d) nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs Reviewed-on: https://chromium-review.googlesource.com/178914 (cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242) Tegra124: nyan: Disable VPR Reviewed-on: https://chromium-review.googlesource.com/179327 (cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d) tegra124: norrin: fix display issue Reviewed-on: https://chromium-review.googlesource.com/179745 (cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb) tegra124: Add iRAM layout information. Reviewed-on: https://chromium-review.googlesource.com/179814 (cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa) tegra124: Run bootblock and ROM stage out of DRAM. Reviewed-on: https://chromium-review.googlesource.com/179822 (cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce) nyan: clean up a comment regarding video Reviewed-on: https://chromium-review.googlesource.com/180161 (cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447) tegra124: norrin: the first step to clean up display code Reviewed-on: https://chromium-review.googlesource.com/180135 (cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d) Squashed 49 commits for tegra124/nyan. Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra/displayport.h | 4 +- src/soc/nvidia/tegra/dp.c | 586 ------------------------------------- src/soc/nvidia/tegra/usb.c | 15 +- 3 files changed, 9 insertions(+), 596 deletions(-) delete mode 100644 src/soc/nvidia/tegra/dp.c (limited to 'src/soc/nvidia/tegra') diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h index 8a57170bf9..0a86c41d9c 100644 --- a/src/soc/nvidia/tegra/displayport.h +++ b/src/soc/nvidia/tegra/displayport.h @@ -171,10 +171,8 @@ enum { #define EDP_PWR_OFF_TO_ON_TIME_MS (500+10) struct tegra_dc_dp_data { - struct tegra_dc *dc; - struct tegra_dc_sor_data *sor; + struct tegra_dc_sor_data sor; void *aux_base; - struct tegra_dc_mode *mode; struct tegra_dc_dp_link_config link_cfg; }; diff --git a/src/soc/nvidia/tegra/dp.c b/src/soc/nvidia/tegra/dp.c deleted file mode 100644 index 28e30c89c4..0000000000 --- a/src/soc/nvidia/tegra/dp.c +++ /dev/null @@ -1,586 +0,0 @@ -/* - * drivers/video/tegra/dc/dp.c - * - * Copyright (c) 2011-2013, NVIDIA Corporation. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "i2c.h" -#include "dc.h" -/* shit. This is broken. */ -#include -// this is really broken. #include -#include - - -extern int dump; -unsigned long READL(void* p); -void WRITEL(unsigned long value, void* p); - -static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) -{ - void *addr = dp->aux_base + (u32)(reg <<2); - u32 reg_val = READL(addr); - return reg_val; -} - -static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, - u32 reg, u32 val) -{ - void *addr = dp->aux_base + (u32)(reg <<2); - WRITEL(val, addr); -} - - -static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp, - u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms) -{ -// unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms); - u32 reg_val = 0; - - printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n", - __func__, reg*4, timeout_ms); - do { -// udelay(poll_interval_us); - udelay(1); - reg_val = tegra_dpaux_readl(dp, reg); - } while (((reg_val & mask) != exp_val) && (--timeout_ms > 0)); - - if ((reg_val & mask) == exp_val) - return 0; /* success */ - printk(BIOS_SPEW,"dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", reg, reg_val, mask, exp_val); - return timeout_ms; -} - - -static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp) -{ - /* According to DP spec, each aux transaction needs to finish - within 40ms. */ - if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, - DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, - DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, - 100, DP_AUX_TIMEOUT_MS*1000) != 0) { - printk(BIOS_SPEW,"dp: DPAUX transaction timeout\n"); - return -1; - } - return 0; -} - -static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 *data, u32 *size, u32 *aux_stat) -{ - int i; - u32 reg_val; - u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; - u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; - u32 temp_data; - - if (*size > DP_AUX_MAX_BYTES) - return -1; /* only write one chunk of data */ - - /* Make sure the command is write command */ - switch (cmd) { - case DPAUX_DP_AUXCTL_CMD_I2CWR: - case DPAUX_DP_AUXCTL_CMD_MOTWR: - case DPAUX_DP_AUXCTL_CMD_AUXWR: - break; - default: - printk(BIOS_SPEW,"dp: aux write cmd 0x%x is invalid\n", - cmd); - return -1; - } - -#if 0 -/* interesting. */ - if (tegra_platform_is_silicon()) { - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { - printk(BIOS_SPEW,"dp: HPD is not detected\n"); - return -EFAULT; - } - } -#endif - - tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); - for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) { - memcpy(&temp_data, data, 4); - tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), - temp_data); - data += 4; - } - - reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); - reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; - reg_val |= cmd; - reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; - reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); - - while ((timeout_retries > 0) && (defer_retries > 0)) { - if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || - (defer_retries != DP_AUX_DEFER_MAX_TRIES)) - udelay(1); - - reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; - tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); - - if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_SPEW,"dp: aux write transaction timeout\n"); - - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - - if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { - if (timeout_retries-- > 0) { - printk(BIOS_SPEW,"dp: aux write retry (0x%x) -- %d\n", - *aux_stat, timeout_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; - } else { - printk(BIOS_SPEW,"dp: aux write got error (0x%x)\n", - *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || - (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { - if (defer_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n", - *aux_stat, defer_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; - } else { - printk(BIOS_SPEW, "dp: aux write defer exceeds max retries " - "(0x%x)\n", - *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == - DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { - *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); - return 0; - } else { - printk(BIOS_SPEW,"dp: aux write failed (0x%x)\n", *aux_stat); - return -1; - } - } - /* Should never come to here */ - return -1; -} - -static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, - u8 *data, u32 *size, u32 *aux_stat) -{ - u32 cur_size = 0; - u32 finished = 0; - u32 cur_left; - int ret = 0; - - do { - cur_size = *size - finished; - if (cur_size > DP_AUX_MAX_BYTES) - cur_size = DP_AUX_MAX_BYTES; - cur_left = cur_size; - ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr, - data, &cur_left, aux_stat); - - cur_size -= cur_left; - finished += cur_size; - addr += cur_size; - data += cur_size; - - if (ret) - break; - } while (*size > finished); - - *size = finished; - return ret; -} - -static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 *data, u32 *size, u32 *aux_stat) -{ - u32 reg_val; - u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; - u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; - - if (*size > DP_AUX_MAX_BYTES) - return -1; /* only read one chunk */ - - /* Check to make sure the command is read command */ - switch (cmd) { - case DPAUX_DP_AUXCTL_CMD_I2CRD: - case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT: - case DPAUX_DP_AUXCTL_CMD_MOTRD: - case DPAUX_DP_AUXCTL_CMD_AUXRD: - break; - default: - printk(BIOS_SPEW,"dp: aux read cmd 0x%x is invalid\n", cmd); - return -1; - } - - if (0){ - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { - printk(BIOS_SPEW,"dp: HPD is not detected\n"); - //return EFAULT; - } - } - - tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); - - reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); - reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; - reg_val |= cmd; - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); - reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; - reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); - while ((timeout_retries > 0) && (defer_retries > 0)) { - if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || - (defer_retries != DP_AUX_DEFER_MAX_TRIES)) - udelay(DP_DPCP_RETRY_SLEEP_NS * 2); - - reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); - tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); - - if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_SPEW,"dp: aux read transaction timeout\n"); - - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat); - - if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { - if (timeout_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n", - *aux_stat, timeout_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; /* retry */ - } else { - printk(BIOS_SPEW,"dp: aux read got error (0x%x)\n", - *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || - (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { - if (defer_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n", - *aux_stat, defer_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; - } else { - printk(BIOS_SPEW,"dp: aux read defer exceeds max retries " - "(0x%x)\n", *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == - DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { - int i; - u32 temp_data[4]; - - for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) - temp_data[i] = tegra_dpaux_readl(dp, - DPAUX_DP_AUXDATA_READ_W(i)); - - *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); - printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size); - memcpy(data, temp_data, *size); - - return 0; - } else { - printk(BIOS_SPEW,"dp: aux read failed (0x%x\n", *aux_stat); - return -1; - } - } - /* Should never come to here */ - printk(BIOS_SPEW, "%s: can't\n", __func__); - return -1; -} - -int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, - u8 *data, u32 *size, u32 *aux_stat) -{ - u32 finished = 0; - u32 cur_size; - int ret = 0; - - do { - cur_size = *size - finished; - if (cur_size > DP_AUX_MAX_BYTES) - cur_size = DP_AUX_MAX_BYTES; - - ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, - data, &cur_size, aux_stat); - - /* cur_size should be the real size returned */ - addr += cur_size; - data += cur_size; - finished += cur_size; - - if (ret) - break; - -#if 0 - if (cur_size == 0) { - printk(BIOS_SPEW,"JZ: no data found, ret\n"); - break; - } -#endif - } while (*size > finished); - - *size = finished; - return ret; -} - -static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, - u8 *data_ptr) -{ - u32 size = 1; - u32 status = 0; - int ret; - - ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - cmd, data_ptr, &size, &status); - if (ret) - printk(BIOS_SPEW,"dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", - cmd, status); - - return ret; -} - -static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *cfg) -{ - u8 dpcd_data; - int ret; - - ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT, - &dpcd_data); - if (ret) - return ret; - - cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK; - printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__, cfg->max_lane_count); - - cfg->support_enhanced_framing = - (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? - 1 : 0; - printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__, cfg->support_enhanced_framing); - - ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD, - &dpcd_data); - if (ret) - return ret; - cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ? - 1 : 0; - printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread); - - ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH, - &cfg->max_link_bw); - if (ret) - return ret; - printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw); - - // jz, changed - // cfg->bits_per_pixel = dp->dc->pdata->default_out->depth; - cfg->bits_per_pixel = 24; - - /* TODO: need to come from the board file */ - /* Venice2 settings */ - cfg->drive_current = 0x20202020; - cfg->preemphasis = 0; - cfg->postcursor = 0; - - ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP, - &dpcd_data); - if (ret) - return ret; - cfg->alt_scramber_reset_cap = - (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ? - 1 : 0; - cfg->only_enhanced_framing = - (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ? - 1 : 0; - printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n", __func__, - cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing); - - cfg->lane_count = cfg->max_lane_count; - cfg->link_bw = cfg->max_link_bw; - cfg->enhanced_framing = cfg->support_enhanced_framing; - return 0; -} - - -//struct tegra_dc dc_data = {0}; -struct tegra_dc_sor_data sor_data = {0}; -struct tegra_dc_dp_data dp_data = {0}; - -static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp, - u8 *rev) -{ - u32 size; - int ret; - u32 status = 0; - - size = 3; - ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - NV_DPCD_REV, rev, &size, &status); - if (ret) { - printk(BIOS_SPEW,"dp: Failed to read NV_DPCD_REV\n"); - return ret; - } - return 0; -} -u32 dp_setup_timing(u32 panel_id, u32 width, u32 height); -void dp_bringup(u32 winb_addr) -{ - struct tegra_dc_dp_data *dp = &dp_data; - - u32 dpcd_rev; - u32 pclk_freq; -// int ret; - - printk(BIOS_SPEW, "JZ: %s: entry\n",__func__); - - dp->sor = &sor_data; -// dp->sor->dc = dc; - dp->sor->base = (void *)TEGRA_ARM_SOR; -// dp->sor->base_res = base_res; -// dp->sor->sor_clk = clk; - dp->sor->link_cfg = &dp->link_cfg; - dp->sor->portnum = 0; - - dp->aux_base = (void *)TEGRA_ARM_DPAUX; -/* dp->mode = 0; */ /* ???? */ - - /* read panel info */ - if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) { - printk(BIOS_SPEW,"PANEL info: \n"); - printk(BIOS_SPEW,"--DPCP version(%#x): %d.%d\n", - dpcd_rev, (dpcd_rev >> 4)&0x0f, (dpcd_rev & 0x0f)); - } - - if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg)) - printk(BIOS_SPEW,"dp: failed to init link configuration\n"); - - dp_link_training((u32)(dp->link_cfg.lane_count), - (u32)(dp->link_cfg.link_bw)); - - pclk_freq = dp_setup_timing(5, 2560, 1700); // W: 2560, H: 1700, use_plld2: 1 - printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n",__func__, pclk_freq); - -// void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr) -void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, - u32 lane_count, u32 enhanced_framing, u32 panel_edp, - u32 pclkfreq, u32 linkfreq); - - dp_misc_setting(dp->link_cfg.bits_per_pixel, - 2560, 1700, winb_addr, - (u32)dp->link_cfg.lane_count, - (u32)dp->link_cfg.enhanced_framing, - (u32)dp->link_cfg.alt_scramber_reset_cap, - pclk_freq, - dp->link_cfg.link_bw * 27); - - -} - -void debug_dpaux_print(u32 addr, u32 size) -{ - struct tegra_dc_dp_data *dp = &dp_data; - u32 status = 0; - u8 buf[16]; - int i; - - if ((size == 0) || (size > 16)) { - printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size); - return; - } - - if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - addr, buf, &size, &status)) { - printk(BIOS_SPEW,"******AuxRead Error: 0x%04x: status 0x%08x\n", addr, status); - return; - } - printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size); - for (i=0; i < size; ++i) - printk(BIOS_SPEW," %02x", buf[i]); - - printk(BIOS_SPEW,"\n"); -} - -int dpaux_read(u32 addr, u32 size, u8 *data) -{ - - struct tegra_dc_dp_data *dp = &dp_data; - u32 status = 0; - - if ((size == 0) || (size > 16)) { - printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size); - return -1; - } - - if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - addr, data, &size, &status)) { - printk(BIOS_SPEW,"dp: Failed to read reg %#x, status: %#x\n", addr, status); - return -1; - } - - return 0; -} - -int dpaux_write(u32 addr, u32 size, u32 data) -{ - struct tegra_dc_dp_data *dp = &dp_data; - u32 status = 0; - int ret; - - printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n", - __func__, addr, size, data); - - ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, - addr, (u8 *)&data, &size, &status); - if (ret) - printk(BIOS_SPEW,"dp: Failed to write to reg %#x, status: 0x%x\n", - addr, status); - return ret; -} - diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 0a3434fb0d..39477e17d3 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -93,13 +93,13 @@ void usb_setup_utmip(struct usb_ctlr *usb) } /* - * Tegra EHCI controllers need their usb_mode and lpm_ctrl registers initialized - * after every EHCI reset and before any other actions (such as Run/Stop bit) - * are taken. We reset the controller here, set those registers and rely on the - * fact that libpayload doesn't reset EHCI controllers on initialization for - * whatever weird reason. This is ugly, fragile, and I really don't like it, but - * making this work will require an ugly hack one way or another so we might as - * well take the path of least resistance for now. + * Tegra EHCI controllers need their usb_mode, lpm_ctrl and tx_fill_tuning + * registers initialized after every EHCI reset and before any other actions + * (such as Run/Stop bit) are taken. We reset the controller here, set those + * registers and rely on the fact that libpayload doesn't reset EHCI controllers + * on initialization for whatever weird reason. This is ugly, fragile, and I + * really don't like it, but making this work will require an ugly hack one way + * or another so we might as well take the path of least resistance for now. */ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type) { @@ -117,4 +117,5 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type) write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */ write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */ + write32(0x10 << 16, &usb->tx_fill_tuning); /* Tx FIFO Burst thresh */ } -- cgit v1.2.3