From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/nvidia/tegra/usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/nvidia/tegra') diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 55d80ed567..2b450c5672 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -149,7 +149,7 @@ void usb_setup_utmip(void *usb_base) int khz = clock_get_pll_input_khz(); /* Stop UTMI+ crystal clock while we mess with its settings */ - clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + clrbits32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ @@ -203,7 +203,7 @@ void usb_setup_utmip(void *usb_base) 25 * khz / 10 << 0); /* TODO: what's this, really? */ udelay(1); - setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + setbits32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ write32(&usb->suspend_ctrl, 1 << 12 | /* UTMI+ enable */ -- cgit v1.2.3