From 759448893c508cd61240b4598336ecdc7f36eba6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Nov 2022 18:19:19 +0100 Subject: soc/nvidia/tegra210: Fix flushing SPI fifo This will avoid clearing the other bits in fifo_status. Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/nvidia/tegra210/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/nvidia/tegra210') diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 0f38df2e6a..e6f667ac71 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -331,7 +331,7 @@ static void flush_fifos(struct tegra_spi_channel *spi) uint32_t fifo_status = read32(&spi->regs->fifo_status); fifo_status |= flush_mask; - write32(&spi->regs->fifo_status, flush_mask); + write32(&spi->regs->fifo_status, fifo_status); while (read32(&spi->regs->fifo_status) & flush_mask) ; -- cgit v1.2.3