From 038e7247dc9705ff2d47dd90ec9a807f6feb52ba Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 29 Jul 2016 18:31:16 +0200 Subject: src/soc: Capitalize CPU, ACPI, RAM and ROM Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth --- src/soc/nvidia/tegra210/include/soc/sdram_param.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/nvidia/tegra210/include') diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 667d090118..dee7c7caab 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -951,9 +951,9 @@ struct sdram_params { /* Set if bit 6 select is greater than bit 7 select; uses aremc. spec packet SWIZZLE_BIT6_GT_BIT7 */ uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot rom write */ + /* Specifies enable and offset for patched boot ROM write */ uint32_t BootRomPatchControl; - /* Specifies data for patched boot rom write */ + /* Specifies data for patched boot ROM write */ uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ -- cgit v1.2.3