From 40a3e321d4e8f2877de1700db67b8c7f7ea89820 Mon Sep 17 00:00:00 2001
From: Patrick Georgi <pgeorgi@chromium.org>
Date: Mon, 22 Jun 2015 19:41:29 +0200
Subject: nvidia/tegra210: add new SoC

This includes Chrome OS downstream up to Change-Id: Ic89ed54c.

Change-Id: I81853434600390d643160fe57554495b2bfe60ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/soc/nvidia/tegra210/i2c6.c | 95 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)
 create mode 100644 src/soc/nvidia/tegra210/i2c6.c

(limited to 'src/soc/nvidia/tegra210/i2c6.c')

diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c
new file mode 100644
index 0000000000..915a5386e9
--- /dev/null
+++ b/src/soc/nvidia/tegra210/i2c6.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/clk_rst.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/padconfig.h>
+#include <soc/power.h>
+
+#define I2C6_PADCTL		0xC001
+#define DPAUX_HYBRID_PADCTL	0x545C0124
+#define DPAUX_HYBRID_SPARE	0x545C0134
+
+static void enable_sor_periph_clocks(void)
+{
+	clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
+
+	/* Give clocks time to stabilize. */
+	udelay(IO_STABILIZATION_DELAY);
+}
+
+static void disable_sor_periph_clocks(void)
+{
+	clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
+
+	/* Give clocks time to stabilize. */
+	udelay(IO_STABILIZATION_DELAY);
+}
+
+static void unreset_sor_periphs(void)
+{
+	clock_clr_reset(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
+}
+
+void soc_configure_i2c6pad(void)
+{
+	/*
+	 * I2C6 on Tegra1xx requires some special init.
+	 * The SOR block must be unpowergated, and a couple of
+	 * display-based peripherals must be clocked and taken
+	 * out of reset so that a DPAUX register can be
+	 * configured to enable the I2C6 mux routing.
+	 * Afterwards, we can disable clocks to the display blocks
+	 * and put Host1X back in reset. DPAUX must remain out of
+	 * reset and the SOR partition must remained unpowergated.
+	 */
+	soc_configure_host1x();
+
+	/* Now we can write the I2C6 mux in DPAUX */
+	write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL);
+	/* Finally, power up the pads */
+	write32((void *)DPAUX_HYBRID_SPARE, 0);
+
+	/*
+	 * Delay before turning off Host1X/DPAUX clocks.
+	 * This delay is needed to keep the sequence from
+	 * hanging the system.
+	 */
+	udelay(CLOCK_PLL_STABLE_DELAY_US);
+
+	/* Stop Host1X/DPAUX clocks and reset Host1X */
+	disable_sor_periph_clocks();
+	clock_set_reset_l(CLK_L_HOST1X);
+}
+
+void soc_configure_host1x(void)
+{
+	power_ungate_partition(POWER_PARTID_SOR);
+
+	/* Host1X needs a valid clock source so DPAUX can be accessed. */
+	clock_configure_source(host1x, PLLP, 204000);
+
+	enable_sor_periph_clocks();
+	remove_clamps(POWER_PARTID_SOR);
+	unreset_sor_periphs();
+}
-- 
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