From 7dcf9d51e5ffadfcf8b5fceddcddb4e1d0a7db37 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 16 Oct 2015 13:10:02 -0700 Subject: arm64: tegra132: tegra210: Remove old arm64/stage_entry.S This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner Reviewed-on: http://review.coreboot.org/12078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/soc/nvidia/tegra210/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/nvidia/tegra210/cpu.c') diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index a837a99cc0..0303150ac6 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -23,7 +23,7 @@ static void enable_core_clocks(int cpu) { - const uint32_t cpu_clocks[CONFIG_MAX_CPUS] = { + const uint32_t cpu_clocks[] = { [0] = CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CX0, [1] = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 | -- cgit v1.2.3