From 8c8e2b7e4c5f1e6a543ce67cf8b47e9feb1bac50 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 14 Oct 2015 10:08:10 -0500 Subject: arm64: remove secmon It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/nvidia/tegra132/Kconfig | 1 - src/soc/nvidia/tegra132/Makefile.inc | 10 --- src/soc/nvidia/tegra132/psci.c | 141 ----------------------------------- src/soc/nvidia/tegra132/secmon.c | 46 ------------ 4 files changed, 198 deletions(-) delete mode 100644 src/soc/nvidia/tegra132/psci.c delete mode 100644 src/soc/nvidia/tegra132/secmon.c (limited to 'src/soc/nvidia/tegra132') diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index ee3b80ea85..4420e52e7c 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -13,7 +13,6 @@ config SOC_NVIDIA_TEGRA132 select HAVE_UART_SPECIAL select ARM_BOOTBLOCK_CUSTOM select SMP - select ARM64_USE_SECURE_MONITOR select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 491b18b5e6..592c34f30a 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -91,16 +91,6 @@ ramstage-y += ramstage.c ramstage-y += mmu_operations.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c -ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c - -secmon-y += 32bit_reset.S -secmon-y += cpu.c -secmon-y += cpu_lib.S -secmon-y += flow_ctrl.c -secmon-y += power.c -secmon-y += psci.c -secmon-y += uart.c -secmon-y += gic.c modules_arm-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra132/psci.c b/src/soc/nvidia/tegra132/psci.c deleted file mode 100644 index 3d6c2100a9..0000000000 --- a/src/soc/nvidia/tegra132/psci.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -static void *cpu_on_entry_point; - -void psci_soc_init(uintptr_t cpu_on_entry) -{ - /* - * Stash secmon entry point for CPUs starting up. The 32-bit reset - * vector register is accessible in < EL3 so one has to attempt to - * plug the potential race for that register being changed out from - * under us. Therefore, we set the appropriate registers here, but - * it is also done on each CPU_ON request. - */ - cpu_on_entry_point = (void *)cpu_on_entry; - cpu_prepare_startup(cpu_on_entry_point); -} - -static size_t children_at_level(int parent_level, uint64_t mpidr) -{ - if (mpidr != 0) - return 0; - - /* T132 just has 2 cores. 0. Level 1 has 2 children at level 0. */ - switch (parent_level) { - case PSCI_AFFINITY_ROOT: - return 1; - case PSCI_AFFINITY_LEVEL_3: - return 1; - case PSCI_AFFINITY_LEVEL_2: - return 1; - case PSCI_AFFINITY_LEVEL_1: - return 2; - case PSCI_AFFINITY_LEVEL_0: - return 0; - default: - return 0; - } -} - -#define TEGRA132_PM_CORE_C7 0x3 - -static inline void tegra132_enter_sleep(unsigned long pmstate) -{ - asm volatile( - " isb\n" - " msr actlr_el1, %0\n" - " wfi\n" - : - : "r" (pmstate)); -} - -static void prepare_cpu_on(int cpu) -{ - uint32_t partid; - - partid = cpu ? POWER_PARTID_CE1 : POWER_PARTID_CE0; - - power_ungate_partition(partid); - flowctrl_write_cpu_halt(cpu, 0); -} - -static int cmd_prepare(struct psci_cmd *cmd) -{ - int ret; - - switch (cmd->type) { - case PSCI_CMD_ON: - prepare_cpu_on(cmd->target->cpu_state.ci->id); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_OFF: - if (cmd->state_id != -1) { - ret = PSCI_RET_INVALID_PARAMETERS; - break; - } - cmd->state_id = TEGRA132_PM_CORE_C7; - ret = PSCI_RET_SUCCESS; - break; - default: - ret = PSCI_RET_NOT_SUPPORTED; - break; - } - return ret; -} - -static int cmd_commit(struct psci_cmd *cmd) -{ - int ret; - struct cpu_info *ci; - - ci = cmd->target->cpu_state.ci; - - switch (cmd->type) { - case PSCI_CMD_ON: - /* Take CPU out of reset */ - start_cpu_silent(ci->id, cpu_on_entry_point); - ret = PSCI_RET_SUCCESS; - break; - case PSCI_CMD_OFF: - flowctrl_cpu_off(ci->id); - tegra132_enter_sleep(cmd->state_id); - /* Never reach here */ - ret = PSCI_RET_NOT_SUPPORTED; - printk(BIOS_ERR, "t132 CPU%d PSCI_CMD_OFF fail\n", ci->id); - break; - default: - ret = PSCI_RET_NOT_SUPPORTED; - break; - } - return ret; -} - -struct psci_soc_ops soc_psci_ops = { - .children_at_level = &children_at_level, - .cmd_prepare = &cmd_prepare, - .cmd_commit = &cmd_commit, -}; diff --git a/src/soc/nvidia/tegra132/secmon.c b/src/soc/nvidia/tegra132/secmon.c deleted file mode 100644 index ea5467d333..0000000000 --- a/src/soc/nvidia/tegra132/secmon.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static void soc_get_secure_mem(uint64_t *base, size_t *size) -{ - uintptr_t tz_base_mib; - size_t tz_size_mib; - - carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); - - tz_base_mib *= MiB; - tz_size_mib *= MiB; - - *base = tz_base_mib; - *size = tz_size_mib; -} - -void soc_get_secmon_base_size(uint64_t *base, size_t *size) -{ - uintptr_t tz_base; - size_t ttb_size, tz_size; - - soc_get_secure_mem(&tz_base, &tz_size); - - ttb_size = TTB_SIZE * MiB; - - *base = tz_base + ttb_size; - *size = tz_size - ttb_size; -} -- cgit v1.2.3