From 9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Fri, 9 Jan 2015 16:54:19 -0800 Subject: uart: pass register width in the coreboot table Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/nvidia/tegra132/uart.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/nvidia/tegra132/uart.c') diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c index 17e1a53d22..3a9ac22584 100644 --- a/src/soc/nvidia/tegra132/uart.c +++ b/src/soc/nvidia/tegra132/uart.c @@ -154,6 +154,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -- cgit v1.2.3