From 732b83ed3667d7c3066d2c16406ab6acdd8f32b9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 9 Jun 2014 13:20:04 -0700 Subject: tegra132: Enable bootblock support in tegra132 including UART support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025 Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/203143 Original-Tested-by: Furquan Shaikh Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Aaron Durbin (cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3) This cherry-pick was modified to match the tegra124 uart.c, which uses the idx and base address calculations instead of Kconfig settings. This driver could use the 8250MEM driver when the ARM vs x86 IO calling convention is worked out. Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6 Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/8517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Aaron Durbin --- src/soc/nvidia/tegra132/sysctr.h | 55 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 src/soc/nvidia/tegra132/sysctr.h (limited to 'src/soc/nvidia/tegra132/sysctr.h') diff --git a/src/soc/nvidia/tegra132/sysctr.h b/src/soc/nvidia/tegra132/sysctr.h new file mode 100644 index 0000000000..ea9746ddf2 --- /dev/null +++ b/src/soc/nvidia/tegra132/sysctr.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SYSCTR_H__ +#define __SOC_NVIDIA_TEGRA132_SYSCTR_H__ + +#include + +enum { + SYSCTR_CNTCR_EN = 1 << 0, + SYSCTR_CNTCR_HDBG = 1 << 1, + SYSCTR_CNTCR_FCREQ = 1 << 8 +}; + +struct sysctr_regs { + uint32_t cntcr; + uint32_t cntsr; + uint32_t cntcv0; + uint32_t cntcv1; + uint8_t _rsv0[0x10]; + uint32_t cntfid0; + uint32_t cntfid1; + uint8_t _rsv1[0xfa8]; + uint32_t counterid4; + uint32_t counterid5; + uint32_t counterid6; + uint32_t counterid7; + uint32_t counterid0; + uint32_t counterid1; + uint32_t counterid2; + uint32_t counterid3; + uint32_t counterid8; + uint32_t counterid9; + uint32_t counterid10; + uint32_t counterid11; +}; +check_member(sysctr_regs, counterid11, 0xffc); + +#endif /* __SOC_NVIDIA_TEGRA132_SYSCTR_H__ */ -- cgit v1.2.3