From 9ba069957b1591628ea4d5e2a9ff8553efa52c71 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Sat, 6 Aug 2016 13:42:37 -0500
Subject: soc/nvidia/tegra132: remove tegra132 support

As no more mainboards are utilizing this SoC support code remove
it. It can be resurrected if ever needed.

BUG=chrome-os-partner:55932

Change-Id: Ic3caf6e6c9b62d012679b996abaa525c8bf679a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16108
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/soc/nvidia/tegra132/romstage.c | 93 --------------------------------------
 1 file changed, 93 deletions(-)
 delete mode 100644 src/soc/nvidia/tegra132/romstage.c

(limited to 'src/soc/nvidia/tegra132/romstage.c')

diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
deleted file mode 100644
index c5c1392c07..0000000000
--- a/src/soc/nvidia/tegra132/romstage.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/cbmem_console.h>
-#include <console/console.h>
-#include <lib.h>
-#include <program_loading.h>
-#include <soc/addressmap.h>
-#include <soc/ccplex.h>
-#include <soc/clock.h>
-#include <soc/sdram.h>
-#include <soc/sdram_configs.h>
-#include <soc/romstage.h>
-#include <symbols.h>
-#include <timer.h>
-#include <timestamp.h>
-
-void __attribute__((weak)) romstage_mainboard_init(void)
-{
-	/* Default empty implementation. */
-}
-
-void romstage(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	exception_init();
-
-	printk(BIOS_INFO, "T132: romstage here\n");
-
-#if CONFIG_BOOTROM_SDRAM_INIT
-	printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n",
-		sdram_get_ram_code());
-#else
-	sdram_init(get_sdram_config());
-	printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
-#endif
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/*
-	 * Trust Zone needs to be initialized after the DRAM initialization
-	 * because carveout registers are programmed during DRAM init.
-	 * cbmem_initialize() is dependent on the Trust Zone region
-	 * initalization because CBMEM lives right below the Trust Zone which
-	 * needs to be properly identified.
-	 */
-	trustzone_region_init();
-
-	/*
-	 * When romstage is running it's always on the reboot path -- never a
-	 * resume path where cbmem recovery is required. Therefore, always
-	 * initialize the cbmem area to be empty.
-	 */
-	cbmem_initialize_empty();
-
-	ccplex_cpu_prepare();
-	printk(BIOS_INFO, "T132 romstage: CPU prepare done\n");
-
-	ccplex_load_mts();
-	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
-
-	romstage_mainboard_init();
-
-	run_ramstage();
-}
-
-void platform_prog_run(struct prog *prog)
-{
-	/* We'll switch to a new stack, so validate our old one here. */
-	checkstack(_estack, 0);
-
-	ccplex_cpu_start(prog_entry(prog));
-
-	clock_halt_avp();
-}
-- 
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