From aa228d08e9b67bd36dd9952e9e0eadc8dbe3a8d9 Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Wed, 23 Jul 2014 17:42:45 -0700 Subject: Tegra132: Configure CPU clock Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible from AVP, the first place that can change CPU clock is after CPU has been brought up, ie, ramstage in this case. CPU initial clock source is set to PLLP by MTS. BUG=None TEST=Norrin64 and A44 Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22 Original-Signed-off-by: Jimmy Zhang Original-Reviewed-on: https://chromium-review.googlesource.com/209698 Original-Reviewed-by: Tom Warren Original-Reviewed-by: Aaron Durbin (cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa) Signed-off-by: Marc Jones Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89 Reviewed-on: http://review.coreboot.org/8677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra132/include/soc/addressmap.h | 3 ++- src/soc/nvidia/tegra132/include/soc/clock.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/nvidia/tegra132/include') diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index 52e4d54356..f5f72db7e4 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -70,7 +70,8 @@ enum { TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, TEGRA_MC_BASE = 0x70019000, TEGRA_EMC_BASE = 0x7001B000, - TEGRA_CSITE_BASE = 0x70040000, + TEGRA_CLUSTER_CLOCK_BASE = 0x70040000, + TEGRA_CSITE_BASE = 0x70800000, TEGRA_SYSCTR0_BASE = 0x700F0000, TEGRA_USBD_BASE = 0x7D000000, TEGRA_USB2_BASE = 0x7D004000, diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h index 6f69fefbc6..5259c18011 100644 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -285,7 +285,7 @@ void clock_external_output(int clk_id); void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq); -void clock_cpu0_config_and_reset(void * entry); +void clock_cpu0_config(void); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_reset_l(u32 l); -- cgit v1.2.3