From 5626d8f59a4a70da4724e778a38e0fe6847fa5d8 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 10 Jul 2014 12:50:27 -0500 Subject: t132: bring up 64-bit denver core The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh Original-Reviewed-by: Stefan Reinauer (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/nvidia/tegra132/include/soc/romstage.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 src/soc/nvidia/tegra132/include/soc/romstage.h (limited to 'src/soc/nvidia/tegra132/include') diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h new file mode 100644 index 0000000000..f9eac26e0d --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/romstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ +#define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ + +void mainboard_configure_pmc(void); +void mainboard_enable_vdd_cpu(void); + +#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ -- cgit v1.2.3